C8051F2XX Datasheet, PDF (71/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
9.3.1. Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved
bits should be set to logic 0. Future product versions may use these bits to implement new features in
which case the reset value of the bit will be logic 0, selecting the feature’s default state. Detailed descrip-
tions of the remaining SFRs are included in the sections of the datasheet associated with their correspond-
ing system function.
SFR Definition 9.1. SP: Stack Pointer
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0x81
Bits 7–0: SP: Stack Pointer.
The stack pointer holds the location of the top of the stack. The stack pointer is incremented
before every PUSH operation. The SP register defaults to 0x07 after reset.
SFR Definition 9.2. DPL: Data Pointer Low Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0x81
Bits 7–0: DPL: Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed RAM.
SFR Definition 9.3. DPH: Data Pointer High Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0x81
Bits 7–0: DPH: Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed RAM.
Rev. 1.6
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