C8051F2XX Datasheet, PDF (136/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
17.2.3. Mode 2: Baud Rate Generator
Timer 2 can be used as a baud rate generator for the serial port (UART) when the UART is operated in
modes 1 or 3 (refer to Section 16.1 for more information on UART operational modes). In Baud Rate Gen-
erator mode, Timer 2 works similarly to the auto-reload mode. On overflow, the 16-bit value held in the two
capture registers (RCAP2H, RCAP2L) is automatically loaded into the counter/timer register. However, the
TF2 overflow flag is not set and no interrupt is generated. Instead, the overflow event is used as the input
to the UART's shift clock. Timer 2 overflows can be used to generate baud rates for transmit and/or
receive independently.
The Baud Rate Generator mode is selected by setting RCLK (T2CON.5) and/or TCLK (T2CON.4) to logic
one. When RCLK or TCLK is set to logic 1, Timer 2 operates in the auto-reload mode regardless of the
state of the CP/RL2 bit. The baud rate for the UART, when operating in mode 1 or 3, is determined by the
Timer 2 overflow rate:
Baud Rate = Timer 2 Overflow Rate / 16.
Note, in all other modes, the time base for the timer is the system clock divided by one or twelve as
selected by the T2M bit in CKCON. However, in Baud Rate Generator mode, the time base is the system
clock divided by two. No other divisor selection is possible. If a different time base is required, setting the
C/T2 bit to logic 1 will allow the time base to be derived from the external input pin T2. In this case, the
baud rate for the UART is calculated as:
Baud Rate = FCLK / [32 x (65536 – [RCAP2H:RCAP2L]) ]
Where FCLK is the frequency of the signal supplied to T2 and [RCAP2H:RCAP2L] is the 16-bit value held
in the capture registers.
As explained above, in Baud Rate Generator mode, Timer 2 does not set the TF2 overflow flag and there-
fore cannot generate an interrupt. However, if EXEN2 is set to logic 1, a high-to-low transition on the T2EX
input pin will set the EXF2 flag and a Timer 2 interrupt will occur if enabled. Therefore, the T2EX input may
be used as an additional external interrupt source.
SYSCLK
T2
Timer 1
Overflow
T2EX
2
PORT0
MUX
0
C/T2
1
TCLK
TL2
TH2
Timer 2
Overflow
TR2
1
PCON
Reload
0
2
S
M
O
D
G
F
1
G
F
0
S
T
O
P
I
D
L
E
RCAP2L RCAP2H
1
0
1
EXEN2
PORT0
MUX
0
CP/RL2
C/T2
TR2
EXEN2
TCLK
RCLK
EXF2
TF2
Interrupt
Figure 17.6. T2 Mode 2 Block Diagram
16
RCLK
16
TCLK
RX Clock
TX Clock
136
Rev. 1.6