C8051F2XX Datasheet, PDF (8/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
Table 9.1. CIP-51 Instruction Set Summary............................................................ 60
Figure 9.2. Memory Map .......................................................................................... 66
Table 9.2. Special Function Register Memory Map ................................................ 68
Table 9.3. Special Function Registers .................................................................... 69
Table 9.4. Interrupt Summary ................................................................................. 75
10. Flash Memory
Table 10.1. Flash Memory Electrical Characteristics ............................................... 86
Figure 10.1. Flash Program Memory Security Bytes................................................ 87
11. On-Chip XRAM (C8051F206/226/236)
12. Reset Sources
Figure 12.1. Reset Sources Diagram ....................................................................... 91
Figure 12.2. VDD Monitor Timing Diagram .............................................................. 92
Table 12.1. VDD Monitor Electrical Characteristics.................................................. 96
13. Oscillator
Figure 13.1. Oscillator Diagram................................................................................ 97
Table 13.1. Internal Oscillator Electrical Characteristics .......................................... 98
14. Port Input/Output
Figure 14.1. Port I/O Functional Block Diagram ..................................................... 102
Figure 14.2. Port I/O Cell Block Diagram ............................................................... 102
Table 14.1. Port I/O DC Electrical Characteristics.................................................. 109
15. Serial Peripheral Interface Bus
Figure 15.1. SPI Block Diagram ............................................................................. 110
Figure 15.2. SPI Block Diagram ............................................................................. 111
Figure 15.3. Full Duplex Operation......................................................................... 112
Figure 15.4. Full Duplex Operation......................................................................... 113
16. UART
Figure 16.1. UART Block Diagram ......................................................................... 117
Table 16.1. UART Modes ....................................................................................... 118
Figure 16.2. UART Mode 0 Interconnect................................................................ 118
Figure 16.3. UART Mode 0 Timing Diagram .......................................................... 118
Figure 16.4. UART Mode 1 Timing Diagram .......................................................... 119
Figure 16.5. UART Modes 1, 2, and 3 Interconnect Diagram ................................ 120
Figure 16.6. UART Modes 2 and 3 Timing Diagram .............................................. 121
Figure 16.7. UART Multi-Processor Mode Interconnect Diagram .......................... 122
Table 16.2. Oscillator Frequencies for Standard Baud Rates ................................ 122
17. Timers
Figure 17.1. T0 Mode 0 Block Diagram.................................................................. 126
Figure 17.2. T0 Mode 2 Block Diagram.................................................................. 127
Figure 17.3. T0 Mode 3 Block Diagram.................................................................. 128
Figure 17.4. T2 Mode 0 Block Diagram.................................................................. 134
Figure 17.5. T2 Mode 1 Block Diagram.................................................................. 135
Figure 17.6. T2 Mode 2 Block Diagram.................................................................. 136
18. JTAG
8
Rev. 1.6