C8051F2XX Datasheet, PDF (141/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
JTAG Register Definition 18.2. FLASHCON: JTAG Flash Control
WRMD3 WRMD2 WRMD1 WRMD0
Bit7
Bit6
Bit5
Bit4
RDMD3
Bit3
RDMD2
Bit2
RDMD1
Bit1
RDMD0
Bit0
Reset Value
00000000
This register determines how the Flash interface logic will respond to reads and writes to the FLASH-
DAT Register.
Bits7–4:
WRMD3–0: Write Mode Select Bits.
The Write Mode Select Bits control how the interface logic responds to writes to the FLASH-
DAT Register per the following values:
0000: A FLASHDAT write replaces the data in the FLASHDAT register, but is otherwise
ignored.
0001: A FLASHDAT write initiates a write of FLASHDAT into the memory address selected
by the FLASHADR register. FLASHADR is incremented by one when complete.
0010: A FLASHDAT write initiates an erasure (sets all bytes to 0xFF) of the Flash page
containing the address in FLASHADR. FLASHDAT must be 0xA5 for the erase to
occur. FLASHADR is not affected. If FLASHADR = 0x1DFE – 0x1DFF, the entire
user space will be erased (i.e. entire Flash memory except for Reserved area
0x1E00 – 0x1FFF).
(All other values for WRMD3–0 are reserved.)
Bits3–0:
RDMD3–0: Read Mode Select Bits.
The Read Mode Select Bits control how the interface logic responds to reads to the FLASH-
DAT Register per the following values:
0000: A FLASHDAT read provides the data in the FLASHDAT register, but is otherwise
ignored.
0001: A FLASHDAT read initiates a read of the byte addressed by the FLASHADR register
if no operation is currently active. This mode is used for block reads.
0010: A FLASHDAT read initiates a read of the byte addressed by FLASHADR only if no
operation is active and any data from a previous read has already been read from
FLASHDAT. This mode allows single bytes to be read (or the last byte of a block)
without initiating an extra read.
(All other values for RDMD3–0 are reserved.)
JTAG Register Definition 18.3. FLASHADR: JTAG Flash Address
Bit15
Reset Value
0x0000
Bit0
This register holds the address for all JTAG Flash read, write, and erase operations. This register
autoincrements after each read or write, regardless of whether the operation succeeded or failed.
Bits15–0: Flash Operation 16-bit Address.
Rev. 1.6
141