C8051F2XX Datasheet, PDF (82/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
SFR Definition 9.13. EIP2: Extended Interrupt Priority 2
R/W
R/W
PXVLD
-
Bit7
Bit6
R/W
PSCI3
Bit5
R/W
PSCI2
Bit4
R/W
PSCI1
Bit3
R/W
PSCI0
Bit2
R/W
PADC0
Bit1
R/W
Reset Value
-
00000000
Bit0 SFR Address:
0xF7
Bit7:
PXVLD: External Clock Source Valid (XTLVLD) Interrupt Priority Control.
This bit sets the priority of the XTLVLD interrupt.
0: XTLVLD interrupt set to low priority level.
1: XTLVLD interrupt set to high priority level.
Bit6: Reserved. Must write 0. Reads 0.
Bit5:
PSCI3: Software Controlled Interrupt 3 Priority Control.
This bit sets the priority of the Software Controlled Interrupt 3.
0: External Interrupt 7 set to low priority level.
1: External Interrupt 7 set to high priority level.
Bit4:
PSCI2: Software Controlled Interrupt 2 Priority Control.
This bit sets the priority of the Software Controlled Interrupt 2.
0: Software Controlled Interrupt 2 set to low priority level.
1: Software Controlled Interrupt 2 set to high priority level.
Bit3:
PSCI1: Software Controlled Interrupt 1 Priority Control.
This bit sets the priority of the Software Controlled Interrupt 1.
0: Software Controlled Interrupt 1 set to low priority level.
1: Software Controlled Interrupt 1 set to high priority level.
Bit2:
PSCI0: Software Controlled Interrupt 0 Priority Control.
This bit sets the priority of the Software Controlled Interrupt 0.
0: Software Controlled Interrupt 0 set to low priority level.
1: Software Controlled Interrupt 0 set to high priority level.
Bit1:
PADC0: ADC End of Conversion Interrupt Priority Control.
This bit sets the priority of the ADC0 End of Conversion Interrupt.
0: ADC0 End of Conversion interrupt set to low priority level.
1: ADC0 End of Conversion interrupt set to high priority level.
Bit0: Reserved. Read = 0, Write = don't care.
82
Rev. 1.6