C8051F2XX Datasheet, PDF (117/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
16. UART
Description
The CIP-51 includes a serial port (UART) capable of asynchronous transmission. The UART can function
in full duplex mode. In all modes, receive data is buffered in a holding register. This allows the UART to
start reception of a second incoming data byte before software has finished reading the previous data byte.
The UART has an associated Serial Control Register (SCON) and a Serial Data Buffer (SBUF) in the
SFRs. The single SBUF location provides access to both transmit and receive registers. Reads access
the Receive register and writes access the Transmit register automatically.
The UART is capable of generating interrupts if enabled. The UART has two sources of interrupts: a
Transmit Interrupt flag, TI (SCON.1) set when transmission of a data byte is complete, and a Receive Inter-
rupt flag, RI (SCON.0) set when reception of a data byte is complete. The UART interrupt flags are not
cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manu-
ally by software. This allows software to determine the cause of the UART interrupt (transmit complete or
receive complete).
PCON
S
M
O
D
SCON
SSSRTRTR
MMME B B I I
012N8 8
SFR Bus
T2CON
RT
CC
LL
KK
Write to
SBUF
Timer 1
Overflow
Timer 2
Overflow
Baud Rate Generation Logic
1
2
0
SMOD
0
16
1
TCLK
SYSCLK
0
16
1
RCLK
32
1
64
0
SMOD
12
00
01
10
11
SM0, SM1
{MODE}
00
01
10
11
TB8
SET
DQ
CLR
SBUF
Zero Detector
Start
Stop Bit
Gen.
Shift
Data
Tx Control
Tx Clock
Serial
Port
Interrupt
Rx Clock
Start
Tx IRQ
TI
Send
REN RB8
RI
Rx IRQ Enable
Rx Control
MSB
Load
SBUF
0x1FF
Shift
Bit Detector
Input Shift Register
(9 bits)
Shift
Load SBUF
SBUF
Read
SBUF
SFR Bus
Figure 16.1. UART Block Diagram
TX
Port0 MUX
P0.0
Port I/O
RX
Port0 MUX
P0.1
Rev. 1.6
117