C8051F2XX Datasheet, PDF (33/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
5.2. ADC Modes of Operation
The ADC has a maximum conversion speed of 100ksps. The ADC conversion clock is derived from the
system clock. The ADC conversion clock is derived from a divided version of SYSCLK. Divide ratios of
1,2,4,8, or 16 are supported by setting the ADCSC bits in the ADC0CF Register. This is useful to adjust
conversion speed to accommodate different system clock speeds.
A conversion can be initiated in one of two ways, depending on the programmed states of the ADC Start of
Conversion Mode bits (ADSTM1, ADSTM0) in ADC0CN. Conversions may be initiated by:
1. Writing a 1 to the ADBUSY bit of ADC0CN;
2. A Timer 2 overflow (i.e., timed continuous conversions).
Writing a 1 to ADBUSY provides software control of the ADC whereby conversions are performed "on-
demand". During conversion, the ADBUSY bit is set to 1 and restored to 0 when conversion is complete.
The falling edge of ADBUSY triggers an interrupt (when enabled) and sets the ADCINT interrupt flag in the
ADC0CN register. Note: When conversions are performed "on-demand", the ADCINT flag, not ADBUSY,
should be polled to determine when the conversion has completed. Converted data is available in the ADC
data word register, ADC0H.
The ADCTM bit in register ADC0CN controls the ADC track-and-hold mode. In its default state, the ADC
input is continuously tracked, except when a conversion is in progress. Setting ADCTM to 1 allows one of
two different low power track-and-hold modes to be specified by states of the ADSTM1-0 bits (also in
ADC0CN):
1. Tracking begins with a write of 1 to ADBUSY and lasts for 3 SAR clocks;
2. Tracking starts with an overflow of Timer 2 and lasts for 3 SAR clocks.
Tracking can be disabled (shutdown) when the entire chip is in low power standby or sleep modes.
A. ADC Timing for External Trigger Source
CNVSTR
(ADSTM[1:0]=10)
SAR Clocks
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
ADCTM=1
Low Power or
Convert
Track
Convert
ADCTM=0
Track Or Convert
Convert
Low Power Mode
Track
B. ADC Timing for Internal Trigger Sources
Timer2, Timer3 Overflow;
Write 1 to ADBUSY
(ADSTM[1:0]=00, 01, 11)
SAR Clocks
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
ADCTM=1
Low Power or
Convert
Track
Convert
SAR Clocks
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Low Power Mode
ADCTM=0 Track or Convert
Convert
Track
Figure 5.2. 12-Bit ADC Track and Conversion Example Timing
Rev. 1.6
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