C8051F2XX Datasheet, PDF (13/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
Digital Power
VDD
GND
TCK
TMS
TDI
TDO
/RST
XTAL1
XTAL2
JTAG
Logic
Emulation HW
8
8kbyte
0
FLASH
5 ^Reset
VDD
Monitor,
WDT
External
Oscillator
Circuit
1
256 byte
SRAM
C
o SFR Bus
r System Clock
Internal
e
Oscillator
Clock & Reset
Configuration
Port I/O Mode
& Config.
Port 0
Latch
P
UART
0
Timer 0
M
U
Timer 1
X
Timer 2
Port 1
Latch
P
CP0+
1
CP0
CP0 _CP0-
M
CP1+
U
CP1
CP1 _CP1-
X
VREF
Comparator
Config.
P
Port 2
2
Latch
SPI
M
U
Port Mux
X
Control
Port 3
Latch
ADC
Config. &
Control
VDD
VREF
A
SAR
M
ADC
U
X
P
0
D
r
v
P
1
D
r
v
P
2
D
r
v
AIN0-AIN21
P0.0/TX
P0.1/RX
P0.2//INT0
P0.3//INT1
P0.4/T0
P0.5/T1
P0.6/T2
P0.7/T2EX
P1.0/CP0+
P1.1/CP0-
P1.2/CP0
P1.3/CP1+
P1.4/CP1-
P1.5/CP1
P1.6/SYSCLK
P1.7
P2.0/SCK
P2.1/MISO
P2.2/MOSI
P2.3/NSS
P2.4
P2.5
VREF
Figure 1.2. C8051F221 Block Diagram (32 LQFP)
Rev. 1.6
13