C8051F2XX Datasheet, PDF (135/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
17.2.2. Mode 1: 16-bit Counter/Timer with Auto-Reload
The Counter/Timer with Auto-Reload mode sets the TF2 timer overflow flag when the counter/timer regis-
ter overflows from 0xFFFF to 0x0000. An interrupt is generated if enabled. On overflow, the 16-bit value
held in the two capture registers (RCAP2H, RCAP2L) is automatically loaded into the counter/timer regis-
ter and the timer is restarted.
Counter/Timer with Auto-Reload mode is selected by clearing the CP/RL2 bit. Setting TR2 to logic 1
enables and starts the timer. Timer 2 can use either the system clock or transitions on an external input pin
as its clock source, as specified by the C/T2 bit. If EXEN2 is set to logic 1, a high-to-low transition on T2EX
will also cause Timer 2 to be reloaded. If EXEN2 is cleared, transitions on T2EX will be ignored.
SYSCLK
T2
T2EX
12
0
1
PORT0
MUX
TR2
EXEN2
PORT0
MUX
CKCON
TTT
210
MMM
0
1
TCLK
TL2
TH2
Reload
RCAP2L RCAP2H
CP/RL2
C/T2
TR2
EXEN2
TCLK
RCLK
EXF2
TF2
Interrupt
Figure 17.5. T2 Mode 1 Block Diagram
Rev. 1.6
135