C8051F2XX Datasheet, PDF (89/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
SFR Definition 10.2. FLSCL: Flash Memory Timing Prescaler
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
FOSE FRAE
-
-
FLASCL
10001111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xB6
Bit7:
Bit6:
Bits5–4:
Bits3–0:
FOSE: Flash One-Shot Timer Enable
0: Flash One-shot timer disabled.
1: Flash One-shot timer enabled
FRAE: Flash Read Always Enable
0: Flash reads per one-shot timer
1: Flash always in read mode
UNUSED. Read = 00b, Write = don't care.
FLASCL: Flash Memory Timing Prescaler.
This register specifies the prescaler value for a given system clock required to generate the
correct timing for Flash write/erase operations. If the prescaler is set to 1111b, Flash
write/erase operations are disabled.
0000: System Clock < 50 kHz
0001: 50 kHz < System Clock < 100 kHz
0010: 100 kHz < System Clock < 200 kHz
0011: 200 kHz < System Clock < 400 kHz
0100: 400 kHz < System Clock < 800 kHz
0101: 800 kHz < System Clock < 1.6 MHz
0110: 1.6 MHz < System Clock < 3.2 MHz
0111: 3.2 MHz < System Clock < 6.4 MHz
1000: 6.4 MHz < System Clock < 12.8 MHz
1001: 12.8 MHz < System Clock < 25.6 MHz
1010: 25.6 MHz < System Clock < 51.2 MHz*
1011, 1100, 1101, 1110: Reserved Values
1111: Flash Memory Write/Erase Disabled
The prescaler value is the smallest value satisfying the following equation:
FLASCL > log2(System Clock / 50kHz)
*For test purposes. The C8051F2xx is not guaranteed to operate over 25 MHz.
SFR Definition 10.3. FLACL: Flash Access Limit
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xB7
Bits 7–0: FLACL: Flash Memory Access Limit.
This register holds the high byte of the 16-bit program memory read/write/erase limit
address. The entire 16-bit access limit address value is calculated as 0xNN00 where NN is
replaced by contents of FLACL. A write to this register sets the Flash Access Limit. Any
subsequent writes are ignored until the next reset.
Rev. 1.6
89