C8051F2XX Datasheet, PDF (17/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
VDD
MonEn
CP0+
CP0-
Comparator 0
+
-
C0RSEF
Supply
Monitor
+
-
Supply
Reset
Timeout
(wired-OR)
/RST
System
Clock
Missing
Clock
Detector
EN
WDT
Reset
Funnel
EN PRE
SWRSF
(Software Reset)
CIP-51 ^{System Reset}
Core
Figure 1.6. Comparison of Peak MCU Throughputs
1.2. On-Board Memory
The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data
RAM, with the upper 128 bytes dual-mapped. An optional 1024 bytes of XRAM is available on the 'F206,
'F226 and 'F236. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and direct
addressing accesses the 128-byte SFR address space. The lower 128 bytes of RAM are accessible via
direct or indirect addressing. The first 32 bytes are addressable as four banks of general purpose regis-
ters, and the next 16 bytes can be byte addressable or bit addressable.
The MCU's program memory consists of 8 k + 128 bytes of Flash. This memory may be reprogrammed in-
system in 512 byte sectors, and requires no special off-chip programming voltage. The 512 bytes from
addresses 0x1E00 to 0x1FFF are reserved for factory use. There is also a user programmable 128-byte
sector at address 0x2000 to 0x207F, which may be useful as a table for storing software constants, nonvol-
atile configuration information, or as additional program space. See Figure 1.7 for the MCU system mem-
ory map.
Rev. 1.6
17