C8051F2XX Datasheet, PDF (32/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
5. ADC (8-Bit, C8051F220/1/6 Only)
Description
The ADC subsystem for the C8051F220/1/6 consists of configurable analog multiplexer (AMUX), a pro-
grammable gain amplifier (PGA), and a 100ksps, 8-bit successive-approximation-register ADC with inte-
grated track-and-hold and programmable window detector (see Figure 5.1). The AMUX, PGA, Data
Conversion Modes, and Window Detector are all configurable under software control via the Special Func-
tion Register's shown in Figure 5.1. The ADC subsystem (ADC, track-and-hold and PGA) is enabled only
when the ADCEN bit in the ADC Control register (ADC0CN, SFR Definition 5.3) is set to 1. The ADC sub-
system is in low power shutdown when this bit is 0.
AIN0-31 are port 0-3
pins -- any external
port pin may be configured as an
analog input
ADC0GTH
ADC0LTH
16
VDD VREF
Dig
Comp
ADWINT
AIN0
AIN31
32-to-1
AMUX
ADCEN
VDD
X
+
-
GND
GND
VDD
8-Bit
SAR
8
ADC
8
T2 OV
ADBUSY(w)
AMX0SL
ADC0CF
ADC0CN
Figure 5.1. 8-Bit ADC Functional Block Diagram
5.1. Analog Multiplexer and PGA
Any external port pin (ports 0-3) may be selected via software. The AMX0SL SFR is used to select the
desired analog input pin. (See SFR Definition 5.1). When the AMUX is enabled, the user selects which
port is to be used (bits PRTSL0-1), and then the pin in the selected port (bits PINSL0-2) to be the analog
input.
The table in ?? shows AMUX functionality by channel for each possible configuration. The PGA amplifies
the AMUX output signal by an amount determined by the states of the AMPGN2-0 bits in the ADC Config-
uration register, ADC0CF (SFR Definition 5.2). The PGA can be software-programmed for gains of 0.5, 1,
2, 4, 8 or 16. It defaults to a gain of 1 on reset.
32
Rev. 1.6