C8051F2XX Datasheet, PDF (108/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
SFR Definition 14.12. P2MODE: Port2 Digital/Analog Input Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
11111111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xF3
Bits7–0: Port2 Digital/Analog Output Mode
0: Corresponding Port2 pin Digital Input disabled. (For analog use, i.e., ADC).
1: Corresponding Port2 pin Digital Input is enabled.
SFR Definition 14.13. P3: Port3 Register*
R/W
P3.7
Bit7
R/W
P3.6
Bit6
R/W
P3.5
Bit5
R/W
P3.4
Bit4
R/W
P3.3
Bit3
R/W
P3.2
Bit2
R/W
P3.1
Bit1
R/W
Reset Value
P3.0
11111111
Bit0
SFR Address:
(bit addressable) 0xB0
Bits7–0:
P3.[7:0]
(Write)
0: Logic Low Output.
1: Logic High Output (high impedance if corresponding PRT3CF.n bit = 0)
(Read)
0: P3.n is logic low.
1: P3.n is logic high.
SFR Definition 14.14. PRT3CF: Port3 Configuration Register*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xA7
Bits7–0: PRT3CF.[7:0]: Output Configuration Bits for P3.7–P3.0 (respectively)
0: Corresponding P3.n Output Mode is Open-Drain.
1: Corresponding P3.n Output Mode is Push-Pull.
108
Rev. 1.6