C8051F2XX Datasheet, PDF (58/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
9. CIP-51 Microcontroller
General Description
The MCU’s system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51^TM instruction set. Standard 803x/805x assemblers and compilers can be used to develop soft-
ware. The MCU has a superset of all the peripherals included with a standard 8051. Included are three
16-bit counter/timers (see description in Section 17), a full-duplex UART (see description in Section 16),
256 bytes of internal RAM, 128 byte Special Function Register (SFR) address space (see Section 9.3),
and four byte-wide I/O Ports (see description in Section 14). The CIP-51 also includes on-chip debug
hardware (see description in Section 18), and interfaces directly with the MCU’s analog and digital sub-
systems providing a complete data acquisition or control-system solution in a single integrated circuit.
Features
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 9.1 for a block diagram).
The CIP-51 includes the following features:
• Fully Compatible with MCS-51 Instruction Set
• 25 MIPS Peak Throughput with 25 MHz Clock
• 0 to 25 MHz Clock Frequency
• 256 Bytes of Internal RAM
• Optional 1024 Bytes of XRAM
• 8 kB Flash Program Memory
• Four Byte-Wide I/O Ports
• Extended Interrupt Handler
• Reset Input
• Power Management Modes
• On-chip Debug Circuitry
• Program and Data Memory Security
DATA BUS
ACCUMULATOR
TMP1
TMP2
PSW
ALU
B REGISTER
STACK POINTER
SRAM
ADDRESS
REGISTER
SRAM
(256 X 8)
DATA BUS
BUFFER
D8
DATA POINTER
D8
PC INCREMENTER
SFR_ADDRESS
SFR
SFR_CONTROL
D8
BUS
SFR_WRITE_DATA
INTERFACE
SFR_READ_DATA
PROGRAM COUNTER (PC)
PRGM. ADDRESS REG.
RESET
CLOCK
CONTROL
LOGIC
PIPELINE
STOP
IDLE
POWER CONTROL
REGISTER
D8
D8
MEM_ADDRESS
MEM_CONTROL
MEMORY
A16
INTERFACE ^{MEM_WRITE_DATA}
MEM_READ_DATA
D8
INTERRUPT
INTERFACE
D8
SYSTEM_IRQs
EMULATION_IRQ
Figure 9.1. CIP-51 Block Diagram
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Rev. 1.6