C8051F2XX Datasheet, PDF (92/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
12.1. Power-on Reset
The CIP-51 incorporates a power supply monitor that holds the MCU in the reset state until V_DD rises
above the VRST level during power-up. (See Figure 12.2 for timing diagram, and refer to Table 12.1 for
the Electrical Characteristics of the power supply monitor circuit.) The RST pin is asserted (low) until the
end of the 100msec V_DD Monitor timeout in order to allow the V_DD supply to become stable. On 48-pin
packages, the V_DD monitor is enabled by pulling the MONEN pin high and is disabled by pulling the
MONEN pin low. The MONEN pin should never be left floating. On 32-pin packages, the V_DD monitor is
always enabled and cannot be disabled.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. All of the other
reset flags in the RSTSRC Register are indeterminate. PORSF is cleared by all other resets. Since all
resets cause program execution to begin at the same location (0x0000), software can read the PORSF
flag to determine if a power-up was the cause of reset. The content of internal data memory should be
assumed to be undefined after a power-on reset.
12.2. Software Forced Reset
Writing a 1 to the PORSF bit forces a Power-On Reset as described in Section 12.1.
2.70
2.55
2.0
1.0
V_RST
t
Logic HIGH
/RST
100ms
100ms
Logic LOW
Figure 12.2. V_DD Monitor Timing Diagram
12.3. Power-fail Reset
When the V_DD monitor is enabled, the MONEN pin (not on C8051F221/F231 32 pin parts) is "pulled high",
and power-down transition or power irregularity causes V_DD to drop below VRST, the power supply monitor
will drive the RST pin low and return the CIP-51 to the reset state (see Figure 12.2). When V_DD returns to
a level above VRST, the CIP-51 will leave the reset state in the same manner as that for the power-on
reset. Note that even though internal data memory contents are not altered by the power-fail reset, it is
impossible to determine if V_DD dropped below the level required for data retention. If the PORSF flag is
set, the data may no longer be valid.
92
Rev. 1.6