C8051F2XX Datasheet, PDF (137/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
SFR Definition 17.8. T2CON: Timer 2 Control
R/W
TF2
Bit7
R/W
EXF2
Bit6
R/W
RCLK
Bit5
R/W
TCLK
Bit4
R/W
EXEN2
Bit3
R/W
TR2
Bit2
R/W
C/T2
Bit1
R/W
Reset Value
CP/RL2 00000000
Bit0
SFR Address:
(bit addressable) 0xC8
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
TF2: Timer 2 Overflow Flag.
Set by hardware when Timer 2 overflows from 0xFFFF to 0x0000. When the Timer 2 inter-
rupt is enabled, setting this bit causes the CPU to vector to the Timer 2 interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
TF2 will not be set when RCLK and/or TCLK are logic 1.
EXF2: Timer 2 External Flag.
Set by hardware when either a capture or reload is caused by a high-to-low transition on the
T2EX input pin and EXEN2 is logic 1. When the Timer 2 interrupt is enabled, setting this bit
causes the CPU to vector to the Timer 2 Interrupt service routine. This bit is not automati-
cally cleared by hardware and must be cleared by software.
RCLK: Receive Clock Flag.
Selects which timer is used for the UART's receive clock in modes 1 or 3.
0: Timer 1 overflows used for receive clock.
1: Timer 2 overflows used for receive clock.
TCLK: Transmit Clock Flag.
Selects which timer is used for the UART's transmit clock in modes 1 or 3.
0: Timer 1 overflows used for transmit clock.
1: Timer 2 overflows used for transmit clock.
EXEN2: Timer 2 External Enable.
Enables high-to-low transitions on T2EX to trigger captures or reloads when Timer 2 is not
operating in Baud Rate Generator mode.
0: High-to-low transitions on T2EX ignored.
1: High-to-low transitions on T2EX cause a capture or reload.
TR2: Timer 2 Run Control.
This bit enables/disables Timer 2.
0: Timer 2 disabled.
1: Timer 2 enabled.
C/T2: Counter/Timer Select.
0: Timer Function: Timer 2 incremented by clock defined by T2M (CKCON.5).
1: Counter Function: Timer 2 incremented by high-to-low transitions on external input pin
P0.6/T2.
CP/RL2: Capture/Reload Select.
This bit selects whether Timer 2 functions in capture or auto-reload mode. EXEN2 must be
logic 1 for high-to-low transitions on T2EX to be recognized and used to trigger captures or
reloads. If RCLK or TCLK is set, this bit is ignored and Timer 2 will function in auto-reload
mode.
0: Auto-reload on Timer 2 overflow or high-to-low transition at T2EX (EXEN2 = 1).
1: Capture on high-to-low transition at T2EX (EXEN2 = 1).
Rev. 1.6
137