M16C6S_09 Datasheet, PDF (98/208 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6S Group
Serial I/O
UART transmit/receive control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UCON
Address
03B016
After reset
X00000002
Bit
symbol
Bit
name
Function
RW
U0IRS UART0 transmit
0 : Transmit buffer empty (Tl = 1)
interrupt cause select bit 1 : Transmission completed (TXEPT = 1)
RW
U1IRS UART1 transmit
0 : Transmit buffer empty (Tl = 1)
interrupt cause select bit 1 : Transmission completed (TXEPT = 1)
RW
U0RRM UART0 continuous
0 : Continuous receive mode disabled
receive mode enable bit 1 : Continuous receive mode enable
RW
U1RRM UART1 continuous
0 : Continuous receive mode disabled
receive mode enable bit 1 : Continuous receive mode enabled
RW
CLKMD0 UART1 CLK/CLKS
Effective when CLKMD1 = “1”
select bit 0
0 : Clock output from CLK1
RW
1 : Clock output from CLKS1
CLKMD1 UART1 CLK/CLKS
0 : CLK output is only CLK1
select bit 1 (Note)
1 : Transfer clock output from multiple pins function
RW
selected
RCSP Separate UART0
CTS/RTS bit
0 : CTS/RTS shared pin
1 : CTS/RTS separated (CTS0 supplied from the P64 pin)
RW
Nothing is assigned. When write, set “0”. When read, its content is indeterminate.
(b7)
Note: When using multiple transfer clock output pins, make sure the following conditions are met:
U1MR register’s CKDIR bit = “0” (internal clock)
UART2 special mode register (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
00 0 0
Symbol
Address
After reset
U0SMR to U2SMR 036F16, 037316, 037716 X00000002
Bit
symbol
Bit
name
IICM I²C mode select bit
Function
0 : Other than I²C mode
1 : I²C mode
ABC Arbitration lost detecting 0 : Update per bit
flag control bit
1 : Update per byte
BBS Bus busy flag
0 : STOP condition detected
1 : START condition detected (busy)
(b3-b6) ^{Reserved bit}
Set to “0”
Nothing is assigned. When write, set “0”. When read, its content is indeterminate.
(b7)
Note 1: The BBS bit is set to “0” by writing “0” in a program. (Writing “1” has no effect.).
RW
RW
RW
RW
(Note1)
RW
Figure 1.13.6. UCON Register and U0SMR to U2SMR Registers
Rev.5.01 Dec 10, 2009 page 98 of 201
REJ03B0014-0501