M16C6S_09 Datasheet, PDF (135/208 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6S Group
SI/O3 and SI/O4
(a) SI/Oi Operation Timing
Figure 1.17.3 shows the SI/Oi operation timing
"H"
SI/Oi internal clock _"L"
CLKi output ^"H"
"L"
Signal written to the "H"
SiTRR register "L"
SOUTi output "H"
"L"
SINi input ^"H"
"L"
1.5 cycle (max) (Note 3)
D0
D1
D2
D3
D4
D5
D6
(Note 2)
D7
SiIC register ^"1"
IR bit "0"
i= 3, 4
Note 1: This diagram applies to the case where the SiC register bits are set as follows:
SMi2=0 (SOUTi output), SMi3=1 (SOUTi output, CLKi function), SMi4=0 (transmit data output at the falling edge and receive data input at the
rising edge of the transfer clock), SMi5=0 (LSB first) and SMi6=1 (internal clock)
Note 2: When the SMi6 bit = 1 (internal clock), the SOUTi pin is placed in the high-impedance state after the transfer finishes.
Note 3: If the SMi6 bit=0 (internal clock), the serial I/O starts sending or receiving data a maximum of 1.5 transfer clock cycles after writing to the
SiTRR register.
Figure 1.17.3. SI/Oi Operation Timing
(b) CLK Polarity Selection
The SiC register's SMi4 bit allows selection of the polarity of the transfer clock. Figure 1.17.4 shows
the polarity of the transfer clock.
(1) When SiC register's SMi4 bit = “0”
CLKi
SINi
SOUTi
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
(Note 2)
(2) When SiC register's SMi4 bit = “1”
CLKi
(Note 3)
SINi
D0 D1 D2 D3 D4 D5 D6 D7
SOUTi
D0 D1 D2 D3 D4 D5 D6 D7
i=3 and 4
Note 1: This diagram applies to the case where the SiC register bits are set as follows:
SMi5=0 (LSB first) and SMi6=1 (internal clock)
Note 2: When the SMi6 bit=1 (internal clock), a high level is output from the CLKi
pin if not transferring data.
Note 3: When the SMi6 bit=1 (internal clock), a low level is output from the CLKi
pin if not transferring data.
Figure 1.17.4. Polarity of Transfer Clock
Rev.5.01 Dec 10, 2009 page 135 of 201
REJ03B0014-0501