M16C6S_09 Datasheet, PDF (79/208 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6S Group
Timer A
Timer A
Figure 1.12.2 shows a block diagram of the timer A. Figures 1.12.3 to 1.12.5 show registers related to the
timer A.
The timer A supports the following four modes. Except in event counter mode, timers A0 to A4 all have the
same function. Use the TMOD1 to TMOD0 bits of TAiMR register (i = 0 to 4) to select the desired mode.
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external device or overflows and underflows of
other timers.
• One-shot timer mode: The timer outputs a pulse only once before it reaches the minimum count
“000016.”
• Pulse width modulation (PWM) mode: The timer outputs pulses in a given width successively.
Select clock
High-Order Bits of Data Bus
Select Count Source
• Timer
• One-Shot Timer
:TMOD1 to TMOD0=00, MR2=0
:TMOD1 to TMOD0=10
f1 or f2 ⁰⁰
• Pulse Width Modulation:TMOD1 to TMOD0=11 _{TMOD1 to TMOD0,}
f8 ⁰¹
MR2
Low-Order Bits of Data Bus
8 low-order
bits
8 high-
order
bits
f32 ¹⁰
TCK1 to TCK0
• Timer(gate function):TMOD1 to TMOD0=00,
MR2=1
Reload Register
Polarity
Selector
TAiIN
00
TAj Overflow ^{(1) 10}
11
TAk Overflow ⁽¹⁾
• Event counter:TMOD1 to TMOD0=01
TAiS
To external
trigger circuit
00
01
11
Decrement
01
Counter
Increment / decrement
Always decrement except
in event counter mode
TAiTGH to TAiTGL
TAiUD
0
TMOD1 to TMOD0
1
TAiOUT
Pulse Output
i=0 to 4
j=i-1, except j=4 if i=0
k=i+1, except k=0 if i=4
NOTES:
1. Overflow or underflow
MR2
Toggle Flip Flop
TAi Addresses
TAj
TAk
Timer A0 0387h - 0386h Timer A4 Timer A1
Timer A1 0389h - 0388h Timer A0 Timer A2
Timer A2 038Bh - 038Ah Timer A1 Timer A3
Timer A3 038Dh - 038Ch Timer A2 Timer A4
Timer A4 038Fh - 038Eh Timer A3 Timer A0
TCK1 to TCK0, TMOD1 to TMOC0, MR2 to MR1 : Bits in TAiMR register
TAiTGH to TAiTGL : Bits in ONSF register if i=0 or bits in TRGSR register if i=1 to 4
TAiS : Bits in the TABSR register
TAiUD : Bits in the UDF register
Figure 1.12.2. Timer A Block Diagram
Timer Ai mode register (i=0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TA0MR to TA4MR
Address
039616 to 039A16
After reset
0016
Bit symbol
Bit name
Function
RW
TMOD0
Operation mode select bit
b1 b0
0 0 : Timer mode
RW
0 1 : Event counter mode
TMOD1
1 0 : One-shot timer mode
1 1 : Pulse width modulation
RW
(PWM) mode
MR0
Function varies with each
RW
MR1
operation mode
RW
MR2
RW
MR3
RW
TCK0
Count source select bit Function varies with each
RW
TCK1
operation mode
RW
Figure 1.12.3. TA0MR to TA4MR Registers
Rev.5.01 Dec 10, 2009 page 79 of 201
REJ03B0014-0501