M16C6S_09 Datasheet, PDF (50/208 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6S Group
Interrupts
Interrupts and Interrupt Vector
One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective
interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the
corresponding interrupt vector. Figure 1.9.2 shows the interrupt vector.
MSB
LSB
Vector address (L)
Low address
Mid address
0000
High address
Vector address (H)
0000
0000
Figure 1.9.2. Interrupt Vector
• Fixed Vector Tables
The fixed vector tables are allocated to the addresses from FFFDC16 to FFFFF16. Table 1.9.1 lists the
fixed vector tables. In the flash memory version of microcomputer, the vector addresses (H) of fixed
vectors are used by the ID code check function. For details, refer to the section "flash memory rewrite
disabling function".
Table 1.9.1. Fixed Vector Tables
Interrupt source
Vector table addresses
Remarks
Reference
Address (L) to address (H)
Undefined instruction FFFDC16 to FFFDF16 Interrupt on UND instruction M16C/60, M16C/20
Overflow
BRK instruction
FFFE016 to FFFE316
FFFE416 to FFFE716
Interrupt on INTO instruction
If the contents of address
FFFE716 is FF16, program ex-
ecution starts from the address
shown by the vector in the
relocatable vector table.
series software
manual
Address match
FFFE816 to FFFEB16
Address match interrupt
Single step (Note) FFFEC16 to FFFEF16
Watchdog timer
FFFF016 to FFFF316
Watchdog timer
Oscillation stop and
re-oscillation detection
________
DBC (Note)
FFFF416 to FFFF716
Clock generating circuit
(Reserved)
FFFF816 to FFFFB16
Reset
FFFFC16 to FFFFF16
Reset
Note: Do not normally use this interrupt because it is provided exclusively for use by development sup-
port tools.
Rev.5.01 Dec 10, 2009 page 50 of 201
REJ03B0014-0501