M16C6S_09 Datasheet, PDF (62/208 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6S Group
Interrupts
Address Match Interrupt
An address match interrupt is generated immediately before executing the instruction at the address indi-
cated by the RMADi register (i=0 to 3). Set the start address of any instruction in the RMADi register. Use
the AIER register’s AIER0 and AIER1 bits and the AIER2 register’s AIER20 and AIER21 bits to enable or
disable the interrupt. Note that the address match interrupt is unaffected by the I flag and IPL. For address
match interrupts, the value of the PC that is saved to the stack area varies depending on the instruction
being executed (refer to Saving Registers).
(The value of the PC that is saved to the stack area is not the correct return address.) Therefore, follow
one of the methods described below to return from the address match interrupt.
• Rewrite the content of the stack and then use the REIT instruction to return.
• Restore the stack to its previous state before the interrupt request was accepted by using the POP or
similar other instruction and then use a jump instruction to return.
Table 1.9.6 shows the value of the PC that is saved to the stack area when an address match interrupt
request is accepted.
Figure 1.9.11 shows the AIER, AIER2, and RMAD0 to RMAD3 registers.
Table 1.9.6. Value of the PC that is saved to the stack area when an address match interrupt
request is accepted
Instruction at the Address Indicated by the RMADi Register
Value of the PC that is
saved to the stack area
• 16-bit op-code instruction
• Instruction shown below among 8-bit operation code instructions
ADD.B:S #IMM8,dest SUB.B:S #IMM8,dest
AND.B:S #IMM8,dest
OR.B:S
#IMM8,dest MOV.B:S #IMM8,dest
STZ.B:S #IMM8,dest
STNZ.B:S #IMM8,dest STZX.B:S #IMM81,#IMM82,dest
CMP.B:S #IMM8,dest PUSHM src
POPM dest
JMPS
#IMM8
JSRS
#IMM8
MOV.B:S #IMM,dest (However, dest=A0 or A1)
The address
indicated by the
RMADi register +2
Instructions other than the above
Value of the PC that is saved to the stack area : Refer to 12.5.7 Saving Registers.
The address
indicated by the
RMADi register +1
Table 1.9.7. Relationship Between Address Match Interrupt Sources and Associated Registers
Address match interrupt sources
Address match interrupt 0
Address match interrupt 1
Address match interrupt 2
Address match interrupt 3
Address match interrupt enable bit
AIER0
AIER1
AIER20
AIER21
Address match interrupt register
RMAD0
RMAD1
RMAD2
RMAD3
Rev.5.01 Dec 10, 2009 page 62 of 201
REJ03B0014-0501