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M16C6S_09 Datasheet, PDF (64/208 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M16C/6S Group
Interrupts
Precautions for Interrupts
(1) Reading Address 0000016
• Do not read the address 0000016 in a program. When a maskable interrupt request is accepted, the
CPU reads interrupt information (interrupt number and interrupt request priority level) from the address
0000016 during the interrupt sequence. At this time, the IR bit for the accepted interrupt is cleared to “0”.
If the address 0000016 is read in a program, the IR bit for the interrupt which has the highest priority
among the enabled interrupts is cleared to “0”. This causes a problem that the interrupt is canceled, or
an unexpected interrupt is generated.
(2) SP Setting
• Set any value in the SP before accepting an interrupt. The SP is cleared to ‘000016’ after reset. There-
fore, if an interrupt is accepted before setting any value in the SP, the program may go out of control.
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(3) INT Interrupt
________
• Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to the INT0
________
through INT3 pins regardless of the CPU clock.
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• When the polarity of the INT0 to INT3 pins is changed, the IR bit is sometimes set to “1” (=interrupt
requested). After changing the polarity, set the IR bit to “0” (=interrupt not requested). Figure 1.9.12
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shows the procedure for changing the INT interrupt generate factor.
(4) Watchdog Timer Interrupt
• Initialize the watchdog timer after the watchdog timer interrupt occurs.
Set the I flag to “0” (=disable interrupt)
Set the ILVL2 to ILVL0 bits to '0002' (= level 0)
(Disable INT interrupt)
Set the POL bit
Set the IR bit to “0” (=interrupt not requested)
Set the ILVL2 to ILVL0 bits to
'0012' (=level 1) to '1112' (=level 7)
(Enable the accepting of INT interrupt request)
Set the I flag to “1” (= enable interrupt)
Note: Execute the setting above individually. Do not execute two or
more settings at once (by one instruction).
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Figure 1.9.12. Switching Procedure for INT Interrupt Request
Rev.5.01 Dec 10, 2009 page 64 of 201
REJ03B0014-0501