M16C6S_09 Datasheet, PDF (122/208 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6S Group
Special Mode
(1) IICM2= 0 (ACK and NACK interrupts), CKPH= 0 (no clock delay)
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
9th bit
SCLi
SDAi
D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK, NACK)
ACK interrupt (DMA1 request),
NACK interrupt
Transfer to UiRB register
b15
b9
•••
b8 b7
b0
D8 D7 D6 D5 D4 D3 D2 D1 D0
UiRB register
(2) IICM2= 0, CKPH= 1 (clock delay)
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
9th bit
SCLi
SDAi
D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK, NACK)
ACK interrupt (DMA1 request),
NACK interrupt
Transfer to UiRB register
b15
b9
•••
b8 b7
b0
D8 D7 D6 D5 D4 D3 D2 D1 D0
UiRB register
(3) IICM2= 1 (UART transmit/receive interrupt), CKPH= 0
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
9th bit
SCLi
SDAi
D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK, NACK)
Receive interrupt _{Transmit interrupt}
(DMA1 request)
Transfer to UiRB register
b15
b9
•••
b8 b7
b0
D0
D7 D6 D5 D4 D3 D2 D1
UiRB register
(4) IICM2= 1, CKPH= 1
1st bit
2nd bit
3rd bit
4th bit
SCLi
5th bit
6th bit
7th bit
8th bit
9th bit
SDAi
D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK, NACK)
Receive interrupt
(DMA1 request)
Transmit interrupt
Transfer to UiRB register Transfer to UiRB register
i=0 to 2
b15
b9
•••
b8 b7
b0
D0
D7 D6 D5 D4 D3 D2 D1
UiRB register
b15
b9
•••
b8 b7
b0
D8 D7 D6 D5 D4 D3 D2 D1 D0
UiRB register
This diagram applies to the case where the following condition is met.
• UiMR register CKDIR bit = 0 (Slave selected)
Figure 1.16.2. Transfer to UiRB Register and Interrupt Timing
Rev.5.01 Dec 10, 2009 page 122 of 201
REJ03B0014-0501