M16C6S_09 Datasheet, PDF (96/208 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6S Group
Serial I/O
UARTi transmit/receive mode register (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After reset
U0MR to U2MR 03A016, 03A816, 037816
0016
Bit
symbol
Bit name
Function
RW
SMD0
Serial I/O mode select bit
b2 b1 b0
0 0 0 : Serial I/O disabled
RW
(Note 2)
0 0 1 : Clock synchronous serial I/O mode
SMD1
0 1 0 : I²C mode
(Note 3)
1 0 0 : UART mode transfer data 7 bits long
RW
SMD2
1 0 1 : UART mode transfer data 8 bits long
1 1 0 : UART mode transfer data 9 bits long
Must not be set except above
RW
CKDIR Internal/external clock
select bit
0 : Internal clock
1 : External clock (Note 1)
(Note 4)
RW
STPS _{Stop bit length select bit} 0 : One stop bit
1 : Two stop bits
RW
PRY Odd/even parity select bit Effective when PRYE = 1
0 : Odd parity
RW
1 : Even parity
PRYE _{Parity enable bit}
0 : Parity disabled
1 : Parity enabled
RW
IOPOL ^{TxD, RxD I/O polarity}
reverse bit
0 : No reverse
1 : Reverse
RW
Note 1: Set the corresponding port direction bit for each CLKi pin to “0” (input mode).
Note 2: To receive data, set the corresponding port direction bit for each RxDi pin to “0” (input mode).
Note 3: Set the corresponding port direction bit for SCL and SDA pins to “0” (input mode).
Note 4: Set “0” to select internal clock of UART2.
UARTi transmit/receive control register 0 (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After reset
U0C0 to U2C0 03A416, 03AC16, 037C16 000010002
Bit
symbol
Bit name
Function
RW
b1 b0
CLK0 BRG count source
0 0 : f1SIO or f2SIO is selected
RW
select bit
0 1 : f8SIO is selected
CLK1
1 0 : f32SIO is selected
1 1 : Must not be set
RW
CRS CTS/RTS function
Effective when CRD = 0
select bit
0 : CTS function is selected (Note 1)
RW
(Note 4)
1 : RTS function is selected
TXEPT Transmit register empty ^{0 : Data present in transmit register (during transmission)}
flag
1 : No data present in transmit register
RO
(transmission completed)
CRD CTS/RTS disable bit ^{0 : CTS/RTS function enabled}
1 : CTS/RTS function disabled
RW
(P60, P64 and P73 can be used as I/O ports)
NCH
Data output select bit
(Note 2)
0 : TxDi/SDAi and SCLi pins are CMOS output
1 : TxDi/SDAi and SCLi pins are N-channel open-drain output
RW
CKPOL CLK polarity select bit
0 : Transmit data is output at falling edge of transfer clock
and receive data is input at rising edge
1 : Transmit data is output at rising edge of transfer clock
RW
and receive data is input at falling edge
UFORM Transfer format select bit 0 : LSB first
RW
(Note 3)
1 : MSB first
Note 1: Set the corresponding port direction bit for each CTSi pin to “0” (input mode).
Note 2: TXD2/SDA2 are N-channel open-drain output. Cannot be set to the CMOS output. NCH bit of U2C0 register is effective in an
output set up of SCL2 pin.
Note 3: Effective for clock synchronous serial I/O mode and UART mode transfer data 8 bits long.
Note 4: CTS1/RTS1 can be used when the UCON register’s CLKMD1 bit = “0” (only CLK1 output) and the UCON register’s RCSP bit =
“0” (CTS0/RTS0 not separated).
Figure 1.13.4. U0MR to U2MR Register and U0C0 to U2C0 Register
Rev.5.01 Dec 10, 2009 page 96 of 201
REJ03B0014-0501