M16C6S_09 Datasheet, PDF (75/208 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6S Group
DMAC
2. DMA Transfer Cycles
Any combination of even or odd transfer read and write addresses is possible. Table 1.11.2 shows the
number of DMA transfer cycles. Table 1.11.3 shows the Coefficient j, k.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k
Table 1.11.2. DMA Transfer Cycles
Transfer unit Access address No. of read
cycles
8-bit transfers
Even
1
(DMBIT= “1”)
Odd
1
16-bit transfers
Even
1
(DMBIT= “0”)
Odd
2
No. of write
cycles
1
1
1
2
Table 1.11.3. Coefficient j, k
Internal ROM, RAM
SFR
No wait With wait 1-wait² 2-wait²
j1
2
2
3
k1
2
2
3
Notes:
1. Depends on the set value of CSE register
2. Depends on the set value of PM20 bit in P
Rev.5.01 Dec 10, 2009 page 75 of 201
REJ03B0014-0501