M16C6S_09 Datasheet, PDF (109/208 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6S Group
UART Mode
Clock Asynchronous Serial I/O (UART) Mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. Table 1.15.1 lists the specifications of the UART mode.
Table 1.15.1. UART Mode Specifications
Item
Specification
Transfer data format
• Character bit (transfer data): Selectable from 7, 8 or 9 bits
• Start bit: 1 bit
• Parity bit: Selectable from odd, even, or none
• Stop bit: Selectable from 1 or 2 bits
Transfer clock
• UiMR(i=0 to 2) register’s CKDIR bit = 0 (internal clock) : fj/ 16(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register 0016 to FF16
• CKDIR bit = “1” (external clock) : fEXT/16(n+1)
(Note 3)
fEXT: Input from CLKi pin. n :Setting value of UiBRG register 0016 to FF16
_______
_______
_______ _______
Transmission, reception control • Selectable from CTS function, RTS function or CTS/RTS function disable
Transmission start condition
• Before transmission can start, the following requirements must be met
_ _{The TE bit of UiC1 register= 1 (transmission enabled)}
_ _{The TI bit of UiC1 register = 0 (data present in UiTB register)}
_______
_______
_ _{If CTS function is selected, input on the CTSi pin = “L”}
Reception start condition
• Before reception can start, the following requirements must be met
_ _{The RE bit of UiC1 register= 1 (reception enabled)}
_ _{Start bit detection}
Interrupt request
generation timing
• For transmission, one of the following conditions can be selected
_ _{The UiIRS bit (Note 2) = 0 (transmit buffer empty): when transferring data from the}
UiTB register to the UARTi transmit register (at start of transmission)
_ _{The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from}
the UARTi transmit register
• For reception
When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
Error detection
• Overrun error (Note 1)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the bit one before the last stop bit of the next data
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered
Select function
• LSB first, MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
• Serial data logic switch
This function reverses the logic of the transmit/receive data. The start and stop bits
are not reversed.
• TXD, RXD I/O polarity switch
This function reverses the polarities of hte TXD pin output and RXD pin input. The
logic levels of all I/O data is reversed.
_______ _______
• Separate CTS/RTS pins (UART0)
_________
_________
CTS0 and RTS0 are input/output from separate pins
Note 1: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC register does not change.
Note 2: The U0IRS and U1IRS bits respectively are the UCON register bits 0 and 1; the U2IRS bit is the U2C1 register bit 4.
Note 3: CKDIR of U2MR must be set “0” to select internal clock.
Rev.5.01 Dec 10, 2009 page 109 of 201
REJ03B0014-0501