M16C6S_09 Datasheet, PDF (107/208 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6S Group
Clock Synchronous serial I/O Mode
(1) When the UiC1 register's UiLCH bit = 0 (no reverse)
Transfer clock ^{“H”}
“L”
TxDi “H”
(no reverse) _{“L”}
D0 D1 D2 D3 D4 D5 D6 D7
(2) When the UiC1 register's UiLCH bit = 1 (reverse)
Transfer clock ^{“H”}
“L”
TxDi “H”
(reverse) _{“L”}
D0 D1 D2 D3 D4 D5 D6 D7
Note: This applies to the case where the UiC0 register’s CKPOL bit = 0
(transmit data output at the falling edge and the receive data
taken in at the rising edge of the transfer clock) and the UFORM
bit = 0 (LSB first).
i = 0 to 1
Figure 1.14.4. Serial Data Logic Switching
(e) Transfer Clock Output From Multiple Pins (UART1)
Use the UCON register’s CLKMD1 to CLKMD0 bits to select one of the two transfer clock output pins.
(See Figure 1.14.5.) This function can be used when the selected transfer clock for UART1 is an
internal clock.
Microcomputer
TXD1 (P67)
CLKS1 (P64)
CLK1 (P65)
IN
CLK
IN
CLK
Transfer enabled
when the UCON
register's
CLKMD0 bit = 0
Transfer enabled
when the UCON
register's
CLKMD0 bit = 1
Note: This applies to the case where the U1MRregister's CKDIR bit
= 0 (internal clock) and the UCON register's CLKMD1 bit = 1 (
transfer clock output from multiple pins).
Figure 1.14.5. Transfer Clock Output From Multiple Pins
Rev.5.01 Dec 10, 2009 page 107 of 201
REJ03B0014-0501