M16C6S_09 Datasheet, PDF (93/208 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6S Group
Serial I/O
Main clock or on-chip oscillator clock
1/2 ^f2SIO
f1SIO
0 ^PCLK1
1
f1SIO or f2SIO
(UART0)
RXD0
RXD polarity
reversing circuit
Clock source selection
CLK1 to CLK0
f1SIO or f2SIO ^00h
f8SIO ^01h
f32SIO ^10h
CKDIR
Internal
0
1
External
U0BRG
register
1 / (n0+1)
1/8
f8SIO
1/4
f32SIO
UART reception SMD2 toSMD0
1/16 ^{010, 100, 101, 110}
Clock synchronous
type
001
Reception
control circuit
Receive
clock
1/16
UART transmission
010, 100, 101, 110
Clock synchronous type
001
Transmission
control circuit
Clock synchronous type
(when internal clock is selected)
1/2
0
Transmit
clock
Transmit/
receive
unit
TXD
polarity
reversing
circuit
TXD0
CLK0
CTS0 /
RTS0
1
CKPOL
CLK
polarity
reversing
circuit
Clock synchronous type
(when internal clock is selected)
Clock synchronous
type
CKDIR
(when external clock
is selected)
CTS/RTS disabled
CTS/RTS selected
1
CRS 0
RCSP
0
VSS
1
RTS0
CTS/RTS disabled
CTS0
1
CTS0 from UART1
0
CRD
n0: Values set to the U0BRG register
PCLK1: Bit in the PCLKR register
SMD2 to SMD0, CKDIR: Bits in U0MR register
CLK1 to CLK0, CKPOL, CRD, CRS: Bits in U0C0 register
CLKMD0, CLKMD1, RCSP: Bits in UCON register
Main clock or on-chip oscillator clock
11//22 ^f2SIO
f1SIO
0 ^PCLK1
1
f1SIO or f2SIO
1/8
f8SIO
(UART1)
RXD1
RXD polarity reversing
circuit
Clock source selection
f1SIO or f2SIO
f8SIO
f32SIO
CLK1 to CLK0 _CKDIR
00
Internal
01
0
10
1
External
U1BRG
register
1 / (n1+1)
1/4
f32SIO
UART reception SMD2 to SMD0
010, 100, 101, 110
1/16
Clock synchronous
type
001
Reception
control circuit
UART transmission
010, 100, 101, 110
1/16
Clock synchronous
type
001
Transmission
control circuit
Receive
clock
Transmit
clock
Transmit/
receive
unit
TXD
polarity
reversing
circuit
TXD1
Clock synchronous type
(when internal clock is selected)
1/2
0
Clock synchronous type
(when external clock is selected))
1
CLK1
CTS1 / RTS1/
CTS0 / CLKS1
CKPOL
CLK
polarity
reversing
circuit
Clock output
pin select
CLKMD0
0
Clock synchronous type
(when internal clock is selected)
1
1 CTS/RTS selected _{CTS/RTS disabled}
CRS ₁
CKDIR
RTS1
0
CLKMD1
VSS
0
1 CTS/RTS disabled
0 CTS1
0
CRD
1
RCSP
CTS0 from UART0
n1: Values set to the U1BRG register
PCLK1: Bit in the PCLKR register
SMD2 to SMD0, CKDIR: Bits in U1MR register
CLK1 to CLK0, CKPOL, CRD, CRS: Bits in U1C0 register
CLKMD0, CLKMD1, RCSP: Bits in UCON register
Main clock or on-chip oscillator clock
1/2 ^f2SIO
f1SIO
0 ^PCLK1
1
f1SIO or f2SIO
1/8
f8SIO
(UART2)
1/4
f32SIO
RXD2
RXD polarity reversing
circuit
Clock source selection
CLK1 to CLK0 _CKDIR
f1SIO or f2SIO ⁰⁰
Internal
f8SIO ⁰¹
0
f32SIO ¹⁰
U2BRG
register
1 / (n2+1)
External
UART reception SMD2 to SMD0
010, 100, 101, 110
1/16
Clock synchronous
type
001
Reception
control circuit
UART transmission
1/16 _{010, 100, 101, 110}
Clock synchronous
type
001
Transmission
control circuit
Clock synchronous type
(when internal clock is selected)
1/2
0
Receive
clock
Transmit
clock
Transmit/
receive
unit
TXD
polarity
reversing
circuit (1)
TXD2
CTS2 /
RTS2
CTS/RTS selected
1
CRS 0
CTS/RTS disabled
VSS _{CTS/RTS disabled}
1
0
CRD
CKDIR
RTS2
CTS2
NOTES :
1. UART2 is the N-channel open-drain output. Cannot be set to the CMOS output.
2. UART2 does not have CLK2 port. So CKDIR must not be set "1."
n2: Values set to the U2BRG register
PCLK1: Bit in the PCLKR register
SMD2 to SMD0, CKDIR: Bits in U2MR register
CLK1 to CLK0, CKPOL, CRD, CRS: Bits in U2C0 register
CLKMD0, CLKMD1, RCSP: Bits in UCON register
Figure 1.13.1. UARTi Block Diagram
Rev.5.01 Dec 10, 2009 page 93 of 201
REJ03B0014-0501