M16C6S_09 Datasheet, PDF (58/208 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6S Group
Interrupts
The operation of saving registers carried out in the interrupt sequence is dependent on whether the
SP^(Note), at the time of acceptance of an interrupt request, is even or odd. If the stack pointer ^(Note) is
even, the FLG register and the PC are saved, 16 bits at a time. If odd, they are saved in two steps, 8 bits
at a time. Figure 1.9.7 shows the operation of the saving registers.
Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indicated
by the U flag. Otherwise, it is the ISP.
(1) SP contains even number
Address
Stack
[SP] – 5 (Odd)
[SP] – 4 (Even)
[SP] – 3(Odd)
[SP] – 2 (Even)
[SP] – 1(Odd)
[SP] (Even)
PCL
PCM
FLGL
FLGH
PCH
Sequence in which order
registers are saved
(2) Saved simultaneously,
all 16 bits
(1) Saved simultaneously,
all 16 bits
Finished saving registers
in two operations.
(2) SP contains odd number
Address
Stack
[SP] – 5 (Even)
[SP] – 4(Odd)
[SP] – 3 (Even)
[SP] – 2(Odd)
[SP] – 1 (Even)
[SP] (Odd)
PCL
PCM
FLGL
FLGH
PCH
Sequence in which order
registers are saved
(3)
(4)
Saved, 8 bits at a time
(1)
(2)
Finished saving registers
in four operations.
PCH : 4 high-order bits of PC
PCM : 8 middle-order bits of PC
PCL : 8 low-order bits of PC
FLGH : 4 high-order bits of FLG
FLGL : 8 low-order bits of FLG
Note: [SP] denotes the initial value of the SP when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Figure 1.9.7. Operation of Saving Register
Rev.5.01 Dec 10, 2009 page 58 of 201
REJ03B0014-0501