M16C6S_09 Datasheet, PDF (104/208 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6S Group
Clock Synchronous serial I/O Mode
(1) Example of transmit timing (when internal clock is selected)
Tc
Transfer clock
“1”
UiC1 register
TE bit
“0”
Write data to the UiTB register
UiC1 register
“1”
TI bit
“0”
“H”
CTSi
“L”
Transferred from UiTB register to UARTi transmit register
TCLK
Stopped pulsing because CTSi = “H”
CLKi
Stopped pulsing because the TE bit = “0”
TxDi
UiC0 register
“1”
TXEPT bit
“0”
SiTIC register
“1”
IR bit
“0”
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
Tc = TCLK = 2(n + 1) / fj
fj: frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
n: value set to UiBRG register
i: 0 to 2
The above timing diagram applies to the case where the register bits are set as follows:
• UiMR register CKDIR bit = 0 (internal clock)
• UiC0 register CRD bit = 0 (CTS/RTS enabled), CRS bit = 0 (CTS selected)
• UiC0 register CKPOL bit = 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock)
• UiRS bit = 0 (an interrupt request occurs when the transmit buffer becomes empty): U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4
(2) Example of receive timing (when external clock is selected)
“1”
UiC1 register
RE bit
“0”
UiC1 register
TE bit
UiC1 register
TI bit
RTSi
CLKi
RxDi
UiC1 register
RI bit
“1”
“0”
Write dummy data to UiTB register
“1”
“0”
Transferred from UiTB register to UARTi transmit register
“H”
Even if the reception is completed, the RTS
“L”
does not change. The RTS becomes “L”
1 / fEXT
when the RI bit changes to “0” from “1”.
Receive data is taken in
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5
Transferred from UARTi receive register
“1”
to UiRB register
“0”
Read out from UiRB register
SiTIC register
“1”
IR bit
“0”
Cleared to “0” when interrupt request is
accepted, or cleared to “0” in a program
The above timing diagram applies to the case where the register bits are set
Make sure the following conditions are met when input
as follows:
to the CLKi pin before receiving data is high:
• UiMR register CKDIR bit = 1 (external clock)
• UiC0 register TE bit = 1 (transmit enabled)
• UiC0 register CRD bit = 0 (CTS/RTS enabled), CRS bit = 1 (RTS selected)
• UiC0 register RE bit = 1 (Receive enabled)
• UiC0 register CKPOL bit = 0 (transmit data output at the falling edge and receive • Write dummy data to the UiTB register
data taken in at the rising edge of the transfer clock)
fEXT: frequency of external clock
Figure 1.14.1. Transmit and Receive Operation
Rev.5.01 Dec 10, 2009 page 104 of 201
REJ03B0014-0501