M16C6S_09 Datasheet, PDF (121/208 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6S Group
Special Mode
Table 1.16.4. I²C Mode Functions
Function
Clock Synchronous Serial I/O I²C Mode (SMD2 to SMD0 = 010b, IICM = 1)
Mode (SMD2 to SMD0 = 001b, _{IICM2 = 0}
IICM = 0)
(NACK/ACK interrupt)
IICM2 = 1
(UART transmit/ receive interrupt)
CKPH = 0
CKPH = 1 CKPH = 0
CKPH = 1
(No clock delay) (Clock delay) (No clock delay) (Clock delay)
Factor of Interrupt Number
6, 7 and 10 ^{(1, 5, 7)}
Start condition detection or stop condition detection
(See Table 1.16.5 STSPSEL Bit Functions)
Factor of Interrupt Number UARTi transmission
15, 17 and 19 ^{(1, 6)}
Transmission started or
completed (selected by UiIRS)
Factor of Interrupt Number UARTi reception
16, 18 and 20 ^{(1, 6)}
When 8th bit received
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
No acknowledgment
detection (NACK)
Rising edge of SCLi 9th bit
Acknowledgment detection
(ACK)
Rising edge of SCLi 9th bit
UARTi transmission ^{UARTi transmission}
Rising edge of
Falling edge of SCLi
SCLi 9th bit
next to the 9th bit
UARTi reception
Falling edge of SCLi 9th bit
Timing for Transferring CKPOL = 0 (rising edge)
Data From the UART
CKPOL = 1 (falling edge)
Reception Shift Register to
the UiRB Register
Rising edge of SCLi 9th bit
Falling edge of
SCLi 9th bit
Falling and rising
edges of SCLi 9th
bit
UARTi Transmission
Output Delay
Not delayed
Delayed
Functions of P6_3, P6_7 TXDi output
and P7_0 Pins
SDAi input/output
Functions of P6_2, P6_6 _{RXDi input}
and P7_1 Pins
SCLi input/output
Functions of P6_1, P6_5 CLKi input or output selected
and P7_2 Pins
(Cannot be used in I²C mode)
Noise Filter Width
15ns
200ns
Read RXDi and SCLi Pin
Levels
Initial Value of TXDi and
SDAi Outputs
Initial and End Values of
SCLi
DMA1 Factor ⁽⁶⁾
Store Received Data
Possible when the
Always possible no matter how the corresponding port direction bit is set
corresponding port direction bit
=0
CKPOL = 0 (H)
CKPOL = 1 (L)
The value set in the port register before setting I²C mode ⁽²⁾
H
L
H
L
UARTi reception
1st to 8th bits of the received
data are stored into bits 7 to 0
in the UiRB register
Acknowledgment detection
(ACK)
UARTi reception
Falling edge of SCLi 9th bit
1st to 8th bits of the received
data are stored into bits 7 to 0
in the UiRB register
1st to 7th bits of the received data are
stored into bits 6 to 0 in the UiRB
register. 8th bit is stored into bit 8 in the
UiRB register.
Read Received Data
The UiRB register status is read
1st to 8th bits are stored
into bits 7 to 0 in the
UiRB register ⁽³⁾
Bits 6 to 0 in the UiRB
register ⁽⁴⁾ are read as
bits 7 to 1. Bit 8 in the
UiRB register is read as
bit 0.
i = 0 to 2
NOTES :
1. If the source or cause of any interrupt is changed, the IR bit in the interrupt control register for the changed interrupt may
inadvertently be set to “1” (interrupt requested). (Refer to Changing the Interrupt Generate Factor.)
If one of the bits shown below is changed, the interrupt source, the interrupt timing, etc. change. Therefore, always be sure to
clear the IR bit to “0” (interrupt not requested) after changing those bits.
SMD2 to SMD0 bits in the UiMR register, IICM bit in the UiSMR register, IICM2 bit in the UiSMR2 register, CKPH bit in the
UiSMR3 register
2. Set the initial value of SDAi output while the SMD2 to SMD0 bits in the UiMR register = 000b (serial I/O disabled).
3. Second data transfer to UiRB register (Rising edge of SCLi 9th bit)
4. First data transfer to UiRB register (Falling edge of SCLi 9th bit)
5. See Figure 1.16.4 STSPSEL Bit Functions.
6. See Figure 1.16.2 Transfer to UiRB Register and Interrupt Timing.
7. When using UART0, be sure to set the IFSR26 bit in the IFSR2A register to “1” (factor of interrupt: UART0 bus collision).
When using UART1, be sure to set the IFSR27 bit to “1” (factor of interrupt: UART1 bus collision).
Rev.5.01 Dec 10, 2009 page 121 of 201
REJ03B0014-0501