M16C6S_09 Datasheet, PDF (97/208 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6S Group
Serial I/O
UARTi transmit/receive control register 1 (i=0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U0C1, U1C1
Address
After reset
03A516,03AD16 000000102
Bit
symbol
Bit name
Function
RW
TE
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
RW
TI
Transmit buffer
empty flag
0 : Data present in UiTB register
1 : No data present in UiTB register
RO
RE Receive enable bit
0 : Reception disabled
RW
1 : Reception enabled
RI
Receive complete flag 0 : No data present in UiRB register
1 : Data present in UiRB register
RO
Nothing is assigned.
(b5-b4) _{When write, set “0”. When read, these contents are “0”.}
UiLCH Data logic select bit
0 : No reverse
1 : Reverse
RW
UiERE Error signal output
enable bit
0 : Output disabled
1 : Output enabled
RW
NOTES:
1. The UiLCH bit is enabled when the SMD2 to SMD0 bits in the UiMR register are set to “001b” (clock synchronous serial I/O
mode), “100b” (UART mode, 7-bit transfer data), or “101b” (UART mode, 8-bit transfer data).
Set this bit to “0” when the SMD2 to SMD0 bits are set to “010b” (I²C mode) or “110b” (UART mode, 9-bit transfer data).
UART2 transmit/receive control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2C1
Address
037D16
After reset
000000102
Bit
symbol
Bit name
Function
RW
TE Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
RW
TI ^{Transmit buffer}
empty flag
0 : Data present in U2TB register
1 : No data present in U2TB register
RO
RE Receive enable bit
0 : Reception disabled
1 : Reception enabled
RW
RI Receive complete flag 0 : No data present in U2RB register
RO
1 : Data present in U2RB register
U2IRS UART2 transmit interrupt 0 : Transmit buffer empty (TI = 1)
cause select bit
1 : Transmit is completed (TXEPT = 1)
RW
U2RRM UART2 continuous
0 : Continuous receive mode disabled
receive mode enable bit 1 : Continuous receive mode enabled
RW
U2LCH Data logic select bit
0 : No reverse
1 : Reverse
RW
U2ERE Error signal output
enable bit
0 : Output disabled
1 : Output enabled
RW
NOTES:
1. The U2LCH bit is enabled when the SMD2 to SMD0 bits in the U2MR registerare set to “001b” (clock synchronous serial I/O
mode), “100b” (UART mode, 7-bit transfer data), or “101b” (UART mode, 8-bit transfer data).
Set this bit to “0” when the SMD2 to SMD0 bits are set to “010b” (I²C mode) or “110b” (UART mode, 9-bit transfer data).
Figure 1.13.5. U0C1 to U2C1 Registers
Rev.5.01 Dec 10, 2009 page 97 of 201
REJ03B0014-0501