M16C6S_09 Datasheet, PDF (119/208 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6S Group
Special Mode
Table 1.16.2. Registers to Be Used and Settings in I²C Mode (1) (Continued)
Register
Bit
Function
UiTB³ 0 to 7
UiRB³ 0 to 7
Master
Set transmission data
Reception data can be read
Slave
Set transmission data
Reception data can be read
8
ACK or NACK is set in this bit
ACK or NACK is set in this bit
ABT
Arbitration lost detection flag
Invalid
OER
Overrun error flag
Overrun error flag
UiBRG 0 to 7
Set a transfer rate
UiMR³ SMD2 to SMD0 Set to ‘0102’
Invalid
Set to ‘0102’
CKDIR
Set to “0”
Set to “1”
IOPOL
Set to “0”
Set to “0”
UiC0 CLK1, CLK0
Select the count source for the UiBRG Invalid
register
CRS
Invalid because CRD = 1
Invalid because CRD = 1
TXEPT
Transmit buffer empty flag
Transmit buffer empty flag
CRD
NCH
Set to “1”
Set to “1”²
Set to “1”
Set to “1”²
CKPOL
Set to “0”
Set to “0”
UFORM
Set to “1”
Set to “1”
UiC1 TE
Set this bit to “1” to enable transmission Set this bit to “1” to enable transmission
TI
Transmit buffer empty flag
Transmit buffer empty flag
RE
Set this bit to “1” to enable reception
Set this bit to “1” to enable reception
RI
U2IRS¹
U2RRM¹,
Reception complete flag
Invalid
Set to “0”
Reception complete flag
Invalid
Set to “0”
UiLCH, UiERE
UiSMR IICM
Set to “1”
Set to “1”
ABC
Select the timing at which arbitration-lost Invalid
is detected
BBS
Bus busy flag
Bus busy flag
3 to 7
Set to “0”
Set to “0”
UiSMR2 IICM2
Refer to Table 1.16.4.
Refer to Table 1.16.4.
CSC
Set this bit to “1” to enable clock
Set to “0”
synchronization
SWC
Set this bit to “1” to have SCLi output Set this bit to “1” to have SCLi output
fixed to “L” at the falling edge of the 9th fixed to “L” at the falling edge of the 9th
bit of clock
bit of clock
ALS
Set this bit to “1” to have SDAi output Set to “0”
stopped when arbitration-lost is detected
STAC
Set to “0”
Set this bit to “1” to initialize UARTi at
start condition detection
SWC2
Set this bit to “1” to have SCLi output Set this bit to “1” to have SCLi output
forcibly pulled low
forcibly pulled low
SDHI
Set this bit to “1” to disable SDAi output Set this bit to “1” to disable SDAi output
7
Set to “0”
Set to “0”
UiSMR3 0, 2, 4 and NODC Set to “0”
Set to “0”
CKPH
Refer to Table 1.16.4
Refer to Table 1.16.4
DL2 to DL0
Set the amount of SDAi digital delay
Set the amount of SDAi digital delay
i=0 to 2
Notes:
1. Set the U0C1 and U1C1 register bit 4 and bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits are
in the UCON register.
2. TxD2 pin is N channel open-drain output. Set the NCH bit in the U2C0 register to “0”.
3. Not all register bits are described above. Set those bits to “0” when writing to the registers in I²C mode.
Rev.5.01 Dec 10, 2009 page 119 of 201
REJ03B0014-0501