M16C6S_09 Datasheet, PDF (133/208 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6S Group
SI/O3 and SI/O4
S I/Oi control register (i = 3, 4) (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
S3C
S4C
Address
036216
036616
After reset
010000016
010000016
Bit
symbol
Bit name
Description
RW
SMi0 Internal synchronous
b1 b0
0 0 : Selecting f1SIO or f2SIO
RW
clock select bit
0 1 : Selecting f8SIO
SMi1
1 0 : Selecting f32SIO
RW
1 1 : Must not be set.
SMi2 SOUTi output disable bit
(Note 4)
0 : SOUTi output
1 : SOUTi output disable(high impedance)
RW
SMi3 S I/Oi port select bit
0 : Input/output port
1 : SOUTi output, CLKi function
RW
SMi4 ^{CLK polarity select bit}
0 : Transmit data is output at falling edge of
transfer clock and receive data is input at
rising edge
1 : Transmit data is output at rising edge of
transfer clock and receive data is input at
falling edge
RW
SMi5 Transfer direction select 0 : LSB first
RW
bit
1 : MSB first
SMi6 Synchronous clock
select bit
0 : External clock ^{(Note 2)}
1 : Internal clock ^{(Note 3)}
RW
SMi7 SOUTi initial value
Effective when SMi3 = 0
set bit
0 : “L” output
RW
1 : “H” output
Note 1: Make sure this register is written to by the next instruction after setting the PRCR register's PRC2 bit to “1”
(write enable).
Note 2: Set the SMi3 bit to “1” (SOUTi output, CLKi function).
Note 3: Set the SMi3 bit to “1” and the corresponding port direction bit to “0” (input mode).
Note 4: Effective when SMi3 bit = 1.
SI/Oi bit rate generator (i = 3, 4) (Notes 1, 2)
b7
b0
Symbol
S3BRG
S4BRG
Address
036316
036716
After reset
Indeterminate
Indeterminate
Description
Assuming that set value = n, BRGi divides the count
source by n + 1
Note 1: Write to this register while serial I/O is neither transmitting nor receiving.
Note 2: Use MOV instruction to write to this register.
Setting range
RW
0016 to FF16
WO
SI/Oi transmit/receive register (i = 3, 4) (Note 1, 2)
b7
b0
Symbol
Address
S3TRR
036016
S4TRR
036416
After reset
Indeterminate
Indeterminate
Description
RW
Transmission/reception starts by writing transmit data to this register. After
transmission/reception finishes, reception data can be read by reading this register.
RW
Note 1: Write to this register while serial I/O is neither transmitting nor receiving.
Note 2: To receive data, set the corresponding port direction bit for SINi to “0” (input mode).
Figure 1.17.2. S3C and S4C Registers, S3BRG and S4BRG Registers, and S3TRR and S4TRR Registers
Rev.5.01 Dec 10, 2009 page 133 of 201
REJ03B0014-0501