M16C6S_09 Datasheet, PDF (118/208 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6S Group
Special Mode
SDAi
Delay
circuit
STPSEL=1
STPSEL=0
ACK=1 ACK=0
ACKD register
Noise
Filter
SDHI _ALS
D _{Q Arbitration}
T
Start condition
detection
Stop condition
detection
Start and stop condition generation block
SDASTSP
SCLSTSP
Transmission
register
UARTi
IICM2=1
IICM=1 and
IICM2=0
Reception register
UARTi
S
Q
Bus
R _busy
IICM2=1
IICM=1 and
IICM2=0
NACK
DMA0, DMA1 request
(UART1: DMA0 only)
UARTi transmit,
NACK interrupt
request
DMA0
(UART0, UART2)
UARTi receive,
ACK interrupt request,
DMA1 request
SCLi
Noise
Filter
Falling edge
detection
IICM=0
R Port register
I/O port _Q (Note)
STPSEL=0
Internal clock
IICM=1UARTi _STPSEL=1
SWC2
External
clock
DQ
T
DQ
T
9th bit
CLK
control
UARTi
ACK
Start/stop condition detection
interrupt request
R
9th bit falling edge
S
SWC
This diagram applies to the case where the UiMR register's SMD2 to SMD0 bits = 0102 and the UiSMR register's IICM bit = 1.
IICM
: Bit in UiSMR register
IICM2, SWC, ALS, SWC2, SDHI : Bit in UiSMR2 register
STSPSEL, ACKD, ACKC
: Bit in UiSMR4 register
i=0 to 2
Note: When the IICM bit =1, the pins can be read even if the direction bit = 1 (output).
Figure 1.16.1. I²C Mode Block Diagram
Rev.5.01 Dec 10, 2009 page 118 of 201
REJ03B0014-0501