M16C6S_09 Datasheet, PDF (113/208 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6S Group
UART Mode
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
UiBRG count
source
UiC1 register
RE bit
RxDi
Transfer clock
UiC1 register
RI bit
RTSi
SiRIC register
IR bit
“1”
“0”
Start bit
Stop bit
D0
D1 D7
Sampled “L”
Receive data taken in
Reception triggered when transfer clock
“1” is generated by falling edge of start bit
“0”
“H”
“L”
“1”
“0”
Transferred from UARTi receive
register to UiRB register
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
The above timing diagram applies to the case where the register bits are set as follows:
• UiMR register PRYE bit = 0 (parity disabled)
• UiMR register STPS bit = 0 (1 stop bit)
• UiC0 register CRD bit = 0 (CTSi/RTSi enabled), CRS bit = 1 (RTSi selected)
i = 0 to 2
Figure 1.15.2. Receive Operation
Bit Rates
In UART mode, the frequency set by the UiBRG register (i=0 to 2) divided by 16 become the bit rates.
Table 1.15.5 lists example of bit rates and settings.
Table 1.15.5. Example of Bit Rates and Settings
Bit Rate
(bps)
1200
2400
4800
9600
14400
19200
28800
Count Source
of BRG
f8
f8
f8
f1
f1
f1
f1
Peripheral Function Clock : 16MHz
Peripheral Function Clock : 24MHz
Set Value of BRG : n Actual Time (bps) Set value of BRG : n Actual Time (bps)
103 (67h)
1202
155 (96h)
1202
51 (33h)
2404
77 (46h)
2404
25 (19h)
4808
38 (26h)
4808
103 (67h)
9615
155 (96h)
9615
68 (44h)
14493
103 (67h)
14423
51 (33h)
19231
77 (46h)
19231
34 (22h)
28571
51 (33h)
28846
31250
f1
31 (1Fh)
31250
47 (2Fh)
31250
38400
f1
25 (19h)
38462
38 (26h)
38462
51200
f1
19 (13h)
50000
28 (1Ch)
51724
Rev.5.01 Dec 10, 2009 page 113 of 201
REJ03B0014-0501