M16C6S_09 Datasheet, PDF (130/208 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6S Group
Special Mode
• Clock Phase Setting Function
One of four combinations of transfer clock phases and polarities can be selected using the UiSMR3
register’s CKPH bit and the UiC0 register’s CKPOL bit.
Make sure the transfer clock polarity and phase are the same for the master and salves to be commu-
nicated.
Figure 1.16.6 shows the transmission and reception timing in master (internal clock).
Figure 1.16.7 shows the transmission and reception timing (CKPH=0) in slave (external clock) while
Figure 1.16.8 shows the transmission and reception timing (CKPH=1) in slave (external clock).
Clock output
"H"
(CKPOL=0, CKPH=0) ^"L"
Clock output
"H"
(CKPOL=1, CKPH=0) "L"
Clock output
"H"
(CKPOL=0, CKPH=1) _"L"
Clock output
"H"
(CKPOL=1, CKPH=1) "L"
Data output timing ^"H"
"L"
Data input timing
D0
D1
D2
D3
D4
D5
D6
D7
Figure 1.16.6. Transmission and Reception Timing in Master Mode (Internal Clock)
Rev.5.01 Dec 10, 2009 page 130 of 201
REJ03B0014-0501