M16C6S_09 Datasheet, PDF (168/208 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6S Group
Flash Memory Version
Flash memory control register 0
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol
FMR0
Address
01B716
After reset
XX0000012
Bit symbol
Bit name
Function
RW
FMR00 RY/BY status flag
0: Busy (being written or erased)
1: Ready
RO
FMR01 ^{CPU rewrite mode select bit 0: Disables CPU rewrite mode}
(Note 1)
1: Inables CPU rewrite mode
RW
FMR02
Lock bit disable select bit
(Note 2)
0: Inables lock bit
1: Disables lock bit
RW
FMSTP ^{Flash memory stop bit}
(Note 3, Note 5))
(b5-b4) ^{Reserved bit}
0: Enables flash memory operation
1: Stops flash memory operation
(placed in low power mode,
RW
flash memory initialized)
Must always be set to “0”
RW
FMR06
Program status flag (Note 4)
0: Terminated normally
1: Terminated in error
RO
FMR07 Erase status flag (Note 4)
0: Terminated normally
1: Terminated in error
RO
Note 1: To set this bit to “1”, write “0” and then “1” in succession. Make sure no interrupts or DMA transfers
will occur before writing “1” after writing “0”. Also, while in EW0 mode, write to this bit from
a program in other than the flash memory.
Note 2: To set this bit to “1”, write “0” and then “1” in succession when the FMR01 bit = 1. Make sure no
interrupts or no DMA transfers will occur before writing “1” after writing “0”.
Note 3: Write to this bit from a program in other than the flash memory.
Note 4: This flag is cleared to “0” by executing the Clear Status command.
Note 5: Effective when the FMR01 bit = 1 (CPU rewrite mode). If the FMR01 bit = 0, although the FMR03 bit
can be set to “1” by writing “1” in a program, the flash memory is neither placed in low power mode
nor initialized.
Flash memory control register 1
b7 b6 b5 b4 b3 b2 b1 b0
0 00
0
Symbol
FMR1
Address
01B516
After reset
0X00XX0X2
Bit symbol
Bit name
Function
RW
(b0)
FMR11
Reserved bit
EW1 mode select bit (
Note)
The value in this bit when read is
RO
indeterminate.
0: EW0 mode
1: EW1 mode
RW
(b3-b2) ^{Reserved bit}
The value in this bit when read is
indeterminate.
RO
(b5-b4) ^{Reserved bit}
Must always be set to “0”
RW
Nothing is assigned.
(b6)
When write, set to “0”. When read, their contents are indeterminate.
(b7)
Reserved bit
Must always be set to “0”
RW
Note : To set this bit to “1”, write “0” and then “1” in succession when the FMR01 bit = 1. Make sure no
interrupts or no DMA transfers will occur before writing “1” after writing “0”.
The FMR01 and FMR11 bits both are cleared to “0” by setting the FMR01 bit to “0”.
Figure 1.21.1. FIDR Register and FMR0 and FMR1 Registers
Rev.5.01 Dec 10, 2009 page 168 of 201
REJ03B0014-0501