M16C6S_09 Datasheet, PDF (57/208 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6S Group
Interrupts
Saving Registers
In the interrupt sequence, the FLG register and PC are saved to the stack.
At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits of the FLG
register, 16 bits in total, are saved to the stack first. Next, the 16 low-order bits of the PC are saved. Figure
1.9.6 shows the stack status before and after an interrupt request is accepted.
The other necessary registers must be saved in a program at the beginning of the interrupt routine. Use
the PUSHM instruction, and all registers except SP can be saved with a single instruction.
Address
MSB
Stack
L SB
m–4
m–3
m–2
m–1
m
Content of previous stack
m + 1 ^{Content of previous stack}
[SP]
SPvalue before
interrupt occurs
Address
MSB
Stack
L SB
m–4
m–3
m–2
PC
L
PC
M
FLGL
m–1
FLGH
PCH
m
Content of previous stack
m + 1 Content of previous stack
[SP]
New SP value
Stack status before interrupt request
is acknowledged
Stack status after interrupt request
is acknowledged
PCH : 4 high-order bits of PC
PCM : 8 middle-order bits of PC
PCL : 8 low-order bits of PC
FLGH : 4 high-order bits of FLG
FLGL : 8 low-order bits of FLG
Figure 1.9.6. Stack Status Before and After Acceptance of Interrupt Request
Rev.5.01 Dec 10, 2009 page 57 of 201
REJ03B0014-0501