M16C6S_09 Datasheet, PDF (59/208 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6S Group
Interrupts
Returning from an Interrupt Routine
The FLG register and PC in the state in which they were immediately before entering the interrupt se-
quence are restored from the stack by executing the REIT instruction at the end of the interrupt routine.
Thereafter the CPU returns to the program which was being executed before accepting the interrupt re-
quest.
Return the other registers saved by a program within the interrupt routine using the POPM or similar in-
struction before executing the REIT instruction.
Interrupt Priority
If two or more interrupt requests are generated while executing one instruction, the interrupt request that
has the highest priority is accepted.
For maskable interrupts (peripheral functions), any desired priority level can be selected using the ILVL2 to
ILVL0 bits. However, if two or more maskable interrupts have the same priority level, their interrupt priority
is resolved by hardware, with the highest priority interrupt accepted.
The watchdog timer and other special interrupts have their priority levels set in hardware. Figure 1.9.8
shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.
________
Reset > DBC > WDT > Peripheral function > Single step > Address match
Figure 1.9.8. Hardware Interrupt Priority
Interrupt Priority Resolution Circuit
The interrupt priority resolution circuit is used to select the interrupt with the highest priority among those
requested.
Figure 1.9.9 shows the circuit that judges the interrupt priority level.
Rev.5.01 Dec 10, 2009 page 59 of 201
REJ03B0014-0501