M16C6S_09 Datasheet, PDF (61/208 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6S Group
Interrupts
______
INT Interrupt
_______
INTi interrupt (i=0 to 3) is triggered by the edges of external inputs. The edge polarity is selected using the
IFSR register's IFSRi bit.
Figure 1.9.10 shows the IFSR and IFSR2A registers.
Interrupt request cause select register
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol
IFSR
Address
035F16
After reset
0016
Bit symbol
IFSR0
Bit name
INT0 interrupt polarity
switching bit
Function
RW
0 : One edge
1 : Both edges (Note 1)
RW
IFSR1
INT1 interrupt polarity
switching bit
0 : One edge
1 : Both edges (Note 1)
RW
IFSR2
IFSR3
INT2 interrupt polarity
switching bit
INT3 interrupt polarity
switching bit
0 : One edge
1 : Both edges (Note 1)
RW
0 : One edge
1 : Both edges (Note 1)
RW
(b5-b4)
Nothing is assigned. When write, set to “0”. When read, its
content is interdeterminate.
IFSR6
Interrupt request cause
select bit
(Note 2)
0 : SI/O3 _{(Note 3)}
1 : reserved
RW
IFSR7
Interrupt request cause
select bit
(Note 2)
0 : SI/O4
1 : reserved
RW
Note 1: When setting this bit to “1” (= both edges), make sure the INT0IC to INT3IC register’s POL bit
is set to “0” (= falling edge).
Note 2: Set this bit to “0” (= SI/O3, SI/O4)
Note 3: When setting this bit to “0” (= SI/O3, SI/O4), make sure the S3IC and S4IC registers’ POL bit is
set to “0” (= falling edge).
Interrupt request cause select register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IFSR2A
Address
035E16
After reset
00XXXXXX2
Bit symbol
Bit name
Function
RW
(b5-b0)
Nothing is assigned. When write, set to “0”.
When read, their contents are indeterminate.
IFSR26
IFSR27
Interrupt request cause
select bit
Interrupt request cause
select bit
0 : reserved
1 : UART0 bus collision
RW
detection
0 : reserved
1 : UART1 bus collision
RW
detection
Figure 1.9.10. IFSR Register and IFSR2A Register
Rev.5.01 Dec 10, 2009 page 61 of 201
REJ03B0014-0501