M16C6S_09 Datasheet, PDF (134/208 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6S Group
SI/O3 and SI/O4
Table 1.17.1. SI/O3 and SI/O4 Specifications
Item
Specification
Transfer data format
• Transfer data length: 8 bits
Transfer clock
• SiC (i=3, 4) register’s SMi6 bit = “1” (internal clock) : fj/ 2(n+1)
fj = f1SIO, f8SIO, f32SIO. n=Setting value of SiBRG register 0016 to FF16.
• SMi6 bit = “0” (external clock) : Input from CLKi pin (Note 1)
Transmission/reception
• Before transmission/reception can start, the following requirements must be met
start condition
Write transmit data to the SiTRR register (Notes 2, 3)
Interrupt request
• When SiC register's SMi4 bit = 0
generation timing
The rising edge of the last transfer clock pulse (Note 4)
• When SMi4 = 1
The falling edge of the last transfer clock pulse (Note 4)
CLKi pin function
I/O port, transfer clock input, transfer clock output
SOUTi pin function
I/O port, transmit data output, high-impedance
SINi pin function
I/O port, receive data input
Select function
• LSB first or MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
• Function for setting an SOUTi initial value set function
When the SiC register's SMi6 bit = 0 (external clock), the SOUTi pin output level while
not transmitting can be selected.
• CLK polarity selection
Whether transmit data is output/input timing at the rising edge or falling edge of
transfer clock can be selected.
Note 1: To set the SiC register’s SMi6 bit to “0” (external clock), follow the procedure described below.
• If the SiC register’s SMi4 bit = 0, write transmit data to the SiTRR register while input on the CLKi pin is
high. The same applies when rewriting the SiC register’s SMi7 bit.
• If the SMi4 bit = 1, write transmit data to the SiTRR register while input on the CLKi pin is low. The same
applies when rewriting the SMi7 bit.
• Because shift operation continues as long as the transfer clock is supplied to the SI/Oi circuit, stop the
transfer clock after supplying eight pulses. If the SMi6 bit = 1 (internal clock), the transfer clock automatically
stops.
Note 2: Unlike UART0 to UART2, SI/Oi (i = 3 to 4) is not separated between the transfer register and buffer. There-
fore, do not write the next transmit data to the SiTRR register during transmission.
Note 3: When the SiC register’s SMi6 bit = 1 (internal clock), SOUTi retains the last data for a 1/2 transfer clock period
after completion of transfer and, thereafter, goes to a high-impedance state. However, if transmit data is
written to the SiTRR register during this period, SOUTi immediately goes to a high-impedance state, with the
data hold time thereby reduced.
Note 4: When the SiC register’s SMi6 bit = 1 (internal clock), the transfer clock stops in the high state if the SMi4 bit
= 0, or stops in the low state if the SMi4 bit = 1.
Rev.5.01 Dec 10, 2009 page 134 of 201
REJ03B0014-0501