M16C6S_09 Datasheet, PDF (77/208 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6S Group
DMAC
Channel Priority and DMA Transfer Timing
If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are
detected active in the same sampling period (one period from a falling edge to the next falling edge of
BCLK), the DMAS bit on each channel is set to “1” (DMA requested) at the same time. In this case, the
DMA requests are arbitrated according to the channel priority, DMA0 > DMA1. The following describes
DMAC operation when DMA0 and DMA1 requests are detected active in the same sampling period.
Figure 1.11.6 shows an example of DMA transfer effected by external factors.
In Figure 1.11.6, because DMA0 and DMA1 requests occurred at the same time, DMA0 which has higher
channel priority is accepted first and a DMA transfer on it starts. When DMA0 finishes one transfer unit, it
relinquishes control of the bus to the CPU, and when the CPU finishes one bus access, DMA1 starts a
transfer next and after completion of one transfer unit, returns control of the bus to the CPU.
Note that because there is only one DMAS bit on each channel, the number of times DMA is requested
cannot be counted. Therefore, even if multiple DMA requests occurred before gaining control of the bus
as in the case of DMA1 in Figure 1.11.6, the DMAS bit is set to “0” when control of the bus is gained and
after completion of one transfer unit, control of the bus is returned to the CPU.
An example where DMA requests for external causes are detected active at the same
BCLK
DMA0
DMA1
CPU
INT0
DMA0
request bit
INT1
DMA1
request bit
Figure 1.11.6. DMA Transfer by External Factors
Obtainment
of the bus
right
Rev.5.01 Dec 10, 2009 page 77 of 201
REJ03B0014-0501