MC68HC705MC4 Datasheet, PDF (93/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
divided by 4 and can be used for various functions including a software input capture.
Extended time periods can be attained using the CTOF function to increment a temporary
RAM storage location thereby simulating a 16-bit (or more) counter.
$09 CTCR7 CTCR6 CTCR5 CTCR4 CTCR3 CTCR2 CTCR1 CTCR0
Figure 11-3: Core Timer Counter Register
The power-on cycle clears the entire counter chain and begins clocking the counter. After
4064 cycles, the power-on reset circuit is released that again clears the counter chain and
allows the device to come out of reset. At this point, if RESET is not asserted, the timer
will start counting up from zero and normal device operation will begin. When RESET is
asserted anytime during operation (other than POR), the counter chain will be cleared.
11.4 CORE TIMER DURING WAIT MODE
The CPU clock halts during the WAIT mode, but the timer remains active. If the interrupts
are enabled, the timer interrupt will cause the processor to exit the WAIT mode.
11.5 CORE TIMER DURING STOP MODE
The core timer is cleared when going into STOP mode. When STOP is exited by an
external interrupt or an external RESET, the internal oscillator will resume, followed by
4064 cycles internal processor stabilization delay. The timer is then cleared and operation
resumes.
MOTOROLA
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Section 11: Core Timer