MC68HC705MC4 Datasheet, PDF (69/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
write. The interlock mechanism extends this principle to multiple registers by preventing
data written to groups of data and/or control registers from affecting the PWM
configuration currently active until all writes are complete. There are several interlock
options from which the user can pick depending upon the change of function desired. The
register interlock mechanism operation is shown diagrammatically in Figure 9-8: PWM
Interlock Mechanisms.
RA = RB
RA = RB
CTL-B
PWMB-D
PWMB-I
PWMx-D
PWMA-I
PWMB-I
CTL-A
PWMA-D
CTL-B
CTL-x
CTL-A
CTL-B
PWMA-I
PWMA-x
CTL-A
CTL-A
= Interlocks satisfied; active registers will be updated at
the end of the current PWM cycle
X = don’t care
Figure 9-8: PWM Interlock Mechanisms
MOTOROLA
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Section 9: Pulse Width Modulator