MC68HC705MC4 Datasheet, PDF (11/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
• Mask, Request, Acknowledge, Edge and Sensitivity (Edge- and
Level-Sensitive or Edge-Sensitive Only) control/status bits for IRQ
Interrupt
• On-Chip Oscillator for Crystal/Ceramic Resonator
• Mask Selectable COP Watchdog System
• Power Saving STOP and WAIT Mode Instructions
(Mask Selectable STOP Instruction Disable)
• Illegal Address Reset
• Steering Diode on RESET Pin to V_DD
RESET
V_DD
V_SS
IRQ/V_PP
PB7
PB6
PB5/RDI
PB4/TDO
COP
CORE TIMER
CPU CONTROL
ALU
68HC05 CPU
CPU REGISTERS
ACCUM
INDEX REG
0 0 0 0 0 0 0 0 1 1 STK PNTR
PROGRAM COUNTER
COND CODE REG 1 1 1 H I N Z C
SRAM - 176 BYTES
USER EPROM/ROM - 3584 BYTES
BOOTSTRAP/SELF-CHECK
ROM-240 BYTES
SCI
REGISTERS
AND LOGIC
INTERNAL
CLOCK
÷2
OSC
16-BIT TIMER
÷4 ^{1 INPUT CAPTURE &}
1 OUTPUT COMPARE
OR
2 INPUT CAPTURES
PORT D LOGIC
DUAL PWM
REGISTERS AND
LOGIC
OSC 1
OSC 2
PD7/TCAP2
PD6/TC-
MP/TCAP1
PC7/V_REFL
PC6/V_REFH
PC5/AD5
PC4/AD4
PC3/AD3
PC2/AD2
PC1/AD1
PC0/AD0
PA7
PA6/PWMB3
PA5/PWMA3
PA4/PWMB2
PA3/PWMA2
PA2/PWMB1
PA1/PWMA1
PA0
Figure 1-1: Block Diagram
MOTOROLA
Page 2
Section 1: Introduction