MC68HC705MC4 Datasheet, PDF (57/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
8.3 INPUT CAPTURES
Registers are used to latch the value of the free-running counter after a defined transition
is sensed by the input capture edge detector (Note: The input capture edge detector
contains a Schmitt trigger to improve noise immunity.) The edge that triggers the counter
transfer is defined by each input edge bit (IEDG1, IEDG2) in register TCR. Dynamically
changing from Capture to Compare function will not affect the contents of the registers.
All of the bits in the Input Capture register pair ICRH / ICRL are readable and are not
altered by the 16-bit timer’s control logic. Writes have no effect. Reset does not affect the
contents of these registers. See Figure 8-8: Input Capture Registers (ICRH1 / ICRL1)
and Figure 8-9: Input Capture Registers (ICRH2 / ICRL2).
7
6
5
4
3
2
1
0
R
ICRH1
$001B _W
ICRH7
R
ICRL1
$001C _W
ICRL7
reset ⇒
X
ICRH6
ICRL6
X
ICRH5
ICRL5
X
ICRH4
ICRL4
X
ICRH3
ICRL3
X
ICRH2
ICRL2
X
ICRH1
ICRL1
X
ICRH0
ICRL0
X
Figure 8-8: Input Capture Registers (ICRH1 / ICRL1)
7
6
5
4
3
2
1
0
R
ICRH2
$0019 _W
ICRH7
ICRH6
ICRH5
ICRH4
ICRH3
ICRH2
ICRH1
ICRH0
R
ICRL2
$001A _W
ICRL7
ICRL6
ICRL5
ICRL4
ICRL3
ICRL2
ICRL1
ICRL0
reset ⇒
X
X
X
X
X
X
X
X
Figure 8-9: Input Capture Registers (ICRH2 / ICRL2)
The result obtained by an input capture will be one more than the value of the free-running
counter on the rising edge of the internal clock preceding the external transition (see
Figure 8-10: State Timing Diagram for Input Capture). This delay is required for
internal synchronization. Resolution is affected by the prescaler, allowing the free-running
counter to increment once every four internal clock cycles.
The contents of the free-running counter are transferred to the input capture registers on
each proper signal transition regardless of the state of the respective Input Capture Flag
bit (ICF1, ICF2) in register TSR, the respective Flag will be set. The input capture registers
always contain the free-running counter value, which corresponds to the most recent input
capture. An interrupt can also accompany a successful input capture if the respective
Input Capture Interrupt Enable bit (ICIE) is set.
MOTOROLA
Page 48
Section 8: 16-Bit Timer