MC68HC705MC4 Datasheet, PDF (56/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
2. Write the MSB of the output compare register pair (OCRH) to inhibit
further compares until the LSB is written.
3. Read the Timer Status Register (TSR) to arm the Output Compare Flag
(OCF).
4. Write the LSB of the output compare register pair (OCRL) to enable the
output compare function and to clear its flag OCF (and interrupt).
5. Unblock interrupts by clearing the I-bit in the CCR.
This procedure prevents the Output Compare Flag bit (OCF) from being set between the
time it is read and the time the output compare registers are updated. A software example
is shown in Figure 8-6: Output Compare Software Initialization Example.
9B
SEI
.
.
.
.
.
.
B6 XX LDA
BE XX LDX
B7 16 STA
B6 13 LDA
BF 17 STX
.
.
.
.
.
.
9A
CLI
.
.
DATAH
DATAL
OCRH
TSR
OCRL
.
.
BLOCK INTERRUPTS
.
.
HI BYTE FOR COMPARE
LO BYTE FOR COMPARE
INHIBIT OUTPUT COMPARE
ARM OCF BIT TO CLEAR
READY FOR NEXT COMPARE
.
.
UNBLOCK INTERRUPTS
Figure 8-6: Output Compare Software Initialization Example
Internal
Clock
16-bit
Free-Running _$0FEB
Counter
$0FEC
$0FED
$0FEE
$0FEF
Compare
Register
CPU writes $0FED
$0FED
Compare
Register
Latch
(Note 1)
Output
Compare Flag
and Output Pin
(Note 2)
NOTES:
(Note 3)
1. The CPU write to the compare register may take place at any time, but a compare occurs only at timer state T01. Thus, up
to a four cycle difference may exist between the write to the compare register and the actual compare.
2. Internal compare takes place during timer state T01.
3. The Output Compare flag bit (OCF) is set at timer state T11, which follows the comparison match ($0FED in this example).
Figure 8-7: State Timing Diagram for Output Compare
Section 8: 16-Bit Timer
MOTOROLA
Page 47