MC68HC705MC4 Datasheet, PDF (92/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
11.1.5 RT1:RT0 - Real Time Interrupt Rate Select
These two bits select one of four taps from the Real Time Interrupt circuit.Table 11-1: RTI
Rates shows the available interrupt rates with several f_OP values. Reset sets these RT0
and RT1, selecting the lowest periodic rate and therefore the maximum time in which to
alter these bits if necessary. Care should be taken when altering RT0 and RT1 if the
time-out period is imminent or uncertain. If the selected tap is modified during a cycle in
which the counter is switching, an RTIF could be missed or an additional one could be
generated. To avoid problems, the COP should be cleared before changing RTI taps.
RT1:RT0
00
01
10
11
Table 11-1: RTI Rates
RTI RATES AT BUS FREQUENCY OF:
16.384 kHz
1s
2s
4s
8s
3.0 MHz
5.5 ms
10.9 ms
21.8 ms
43.75 ms
Div. Ratio
2¹⁴
2¹⁵
2¹⁶
2¹⁷
11.2 COMPUTER OPERATING PROPERLY (COP) WATCHDOG RESET
The COP watchdog timer function is implemented on this device by using the output of
the RTI circuit and further dividing it by eight. The minimum COP reset rates are listed in
11.3: CTIMER COUNTER REGISTER (CTCR) $09. If the COP circuit times out, an
internal reset is generated and the normal reset vector is fetched. Preventing a COP
time-out is done by writing a ‘0’ to bit 0 of address $0FF0. When the COP is cleared, only
the final divide by eight stage (output of the RTI) is cleared. This function is a mask option.
Table 11-2: Minimum COP Reset Times
MINIMUM COP RESET AT Bus FREQUENCY:
RT1:RT0
00
16.384 kHz
7s
3.0 MHz
38.2 ms
f_op
7 × (RTI RATE)
01
14 s
76.5 ms
7 × (RTI RATE)
10
28 s
153.0 ms
7 × (RTI RATE)
11
56 s
305.9 ms
7 × (RTI RATE)
11.3 CTIMER COUNTER REGISTER (CTCR) $09
The Core Timer Counter Register is a read-only register that contains the current value of
the 8-bit ripple counter at the beginning of the timer chain. This counter is clocked at f_op
Section 11: Core Timer
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