MC68HC705MC4 Datasheet, PDF (64/99 Pages) Motorola, Inc – Microcontrollers

MC68HC705MC4 Specification Rev. 1.5
of these registers are transferred. This sequence of accesses is referred to as a register
interlock mechanism, and is intended to allow more than one register to be modified
before effecting the PWM operation. The data register interlock mechanism is managed
by mapped each data register to an Interlock address (PWMx-I) and a Direct address
(PWMx-D). Writes to the Interlock address will engage the interlock mechanism. Writes
to the Direct address will not engage the interlock mechanism unless they are already
engaged prior to the write.
9.2 PWM CONTROL BITS
The PWM subsystem is controlled through three control registers: CTL-A, CTL-B, RATE,
and UPDATE. CTL-A, CTL-B, and the Data registers feature a write interlock and buffer
mechanism to permit their contents to be updated simultaneously, preventing undesirable
glitching of the associated Port A I/O.
The RATE register selects the PWM counter input clock rate, defining the PWM period.
This register is buffered but not interlocked with other registers, so writes to this register
will become effective at the end of the current PWM period (if the update bit has been
cleared), irrespective of the state of any interlock mechanism.
9.2.1 POLx - POLARITY
Initializes PWM output. Toggles at Match point to Data Register. See Figure 9-4: PWM
Waveforms (POLx = 1) and Figure 9-5: PWM Waveforms (POLx = 0).
1 = Initialize output to one. Toggles to zero at data match.
0 = Initialize output to zero. Toggles to one at data match.
T
50
FF
80
PWM register = $00
Figure 9-4: PWM Waveforms (POLx = 1)
Section 9: Pulse Width Modulator
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